06-09-2020 08:37 AM
I am using a netlist synthesized in Synplify for a portion of my design. The netlist is added to Vivado as a .vm file (Verilog netlist). The rest of the design is in Vivado, using the typical "IP Integrator" flow. This is for a Kintex Ultrascale part.
During Implementation, I am unable to achieve timing closure. There are hold violations in paths internal to this Synplify netlist. What’s curious is the hold time violations are constant for these nets that are failing, even after tweaking certain things like Implementation strategies and clock uncertainty parameters. It seems like the tool is not even attempting hold fixes.
Xilinx support has advised me that Vivado sees a Synplify netlist the same as its own, and this shouldn't impact whether hold fixes are applied or not. I was also advised to look for "DONT_TOUCH" or "MARK_DEBUG" attributes that may be preventing fixes, however, I have found none.
Does anyone know of any interactions between Synplify or Vivado that would prevent this? Any settings to tweak? Any help or insight would be greatly appreciated!
06-09-2020 08:45 AM - edited 06-09-2020 08:46 AM
Is the clock with hold errors external or generated within Synplify netlist ?
06-09-2020 10:01 AM
Have checked if the clock network is connected to a clock buffer ?
06-10-2020 06:30 AM
I will add, regarding the data path: the source primitive is SRLC32E (32-bit shift register LUT), there is routing (net) delay, and the destination primitive is SRL16E (16-bit shift register LUT)