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9,062 Views
Registered: ‎07-26-2013

Hold Violation for input data register in IOB in source synchronous design

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Hello,

  I have a source synchronous data path (Single data rate) input to the FPGA. I constrain the input path as follows

set_input_delay -clock fxt_clk 0 [get_ports fxt_rx_bus*]

 

The set_input_delay is chosen as 0,as i am assuming the data and clock path delays outside the FPGA are same (due to length matching).

 

The input data is registered in FPGA and placed in IOB registers.

 

I get HOLD violations of around 5ns as the delay in datapath consist only the input pad delay (IBUF) and no routing delay before registering in IOB flop.

 

The clock delay however is huge as it goes through IBUF --> (routing) ---> BUFG  --> (routning) --> IOB Flop clock pin.

 

Even having the PLL in clock path did not help as the PLL did not put enough -ve delay (compensation) in clock path to reduce clock path delay enough.

The PLL had internal feedback through BUFG and compensation attribute set to "External".

 

Virtex7 FPGA with Vivado 2013.3

 

May i know what is wrong in my arrangement? Suggestions please.

 

Thanks,

Sachin

 

 

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Highlighted
15,493 Views
Registered: ‎07-26-2013

Hi,

 As per clocking ug,

ZHOLD: Indicates the PLL is
configured to provide a negative
hold time at the I/O registers.
EXTERNAL: Indicates a network
external to the FPGA is being
compensated.
INTERNAL: Indicates the MMCM
is using its own internal feedback
path so no delay is being
compensated.

 

In my case the clock is coming from external chip (which is same as data source), so isnt the PLL supposed to compensate external clock delay (despite having internal feedback)?

 

I just tried ZHOLD, and it actually did not give any Hold Slack.

 

But i am not yet convinced that external should be used only if external feedback is given to PLL.

I always thought external attribute is same as source synchronous DESKEW attribute of older FPGAs.

 

-Sachin

 

 

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Xilinx Employee
Xilinx Employee
9,054 Views
Registered: ‎05-14-2008

Why do you set the PLL compensation mode to "External"? If you use this mode, you need to set the external feedback path delay by using "set_external_delay" constraint for correct calculation of the PLL compensation delay in timing analysis. As far as I see, you don't need to use the "External" mode for your application.

 

If setup is met but hold is not after using PLL and correctly setting the compensation mode, you can use the phase shifting feature of PLL to move the clock edge to the center of the data window. This will reduce the setup slack but increase the hold slack. If the "setup slack + hold slack" is a positive value, moving the clock edge to the center of the data window will meet both setup and hold at the same time.

 

A kindly remind: having the same trace length on board between the data and clock doesn't mean the input delay is 0, unless the skew between the data and clock is 0 when they go out of the source device. The correct timing analysis is based on correct constraint.

 

Thanks

Vivian

 

 

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Highlighted
15,494 Views
Registered: ‎07-26-2013

Hi,

 As per clocking ug,

ZHOLD: Indicates the PLL is
configured to provide a negative
hold time at the I/O registers.
EXTERNAL: Indicates a network
external to the FPGA is being
compensated.
INTERNAL: Indicates the MMCM
is using its own internal feedback
path so no delay is being
compensated.

 

In my case the clock is coming from external chip (which is same as data source), so isnt the PLL supposed to compensate external clock delay (despite having internal feedback)?

 

I just tried ZHOLD, and it actually did not give any Hold Slack.

 

But i am not yet convinced that external should be used only if external feedback is given to PLL.

I always thought external attribute is same as source synchronous DESKEW attribute of older FPGAs.

 

-Sachin

 

 

View solution in original post

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