11-28-2020 10:29 AM
11-28-2020 12:00 PM
If they both are from the same MMCM, they are perfectly synchronous and therefore when you sample one clock signal with the other clock signal, you sample a signal which is also going at this exact time from 0 to 1 or 1 to 0. So you have a hold violation.
But what an idea to do such a design... I can't figure out what you're trying to achieve.
11-28-2020 12:06 PM
11-28-2020 01:13 PM
This question has basically already been answered. You have the D input of a flip-flop (or in this case SRL) driven by a clock. This is a violation of normal synchronous design practices that causes all kinds of static timing problems.
In general we don't do this - there are almost always ways of accomplishing what you want to do without using structures like this.
But, without knowing what the goal of this structure is, there is no way for us to advise you. In general the two options are to:
As you have already told us that this is not your design, and you have no idea what this thing does, there is no way anyone is going to be able to help you - no matter how you rephrase the question or which aspect of this illegal structure you ask about (setup, hold, structural violation).
There is no other choice - you either need to find the person that wrote this and find out what it supposed to do or reverse engineer the design to figure out what it is supposed to do. Without this, no one can solve this problem and you need to simply throw the design away.