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Adventurer
Adventurer
615 Views
Registered: ‎11-18-2017

Hold time path vs Setup time path

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Hello.

I'm using "Reporting Timing Summary" in Implementation (Vivado) to check out the delays.

Although it is the same path, there was 2 delays; Hold and Setup.

Below figure is the timing report(hold & setup) with the same path.

(Left side is hold and right side is setup)

fig1.png

 

Why is the Hold time path delay more shorter than the Setup time path delay?

Thanks for your help.

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1 Solution

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Moderator
Moderator
594 Views
Registered: ‎03-16-2017

Re: Hold time path vs Setup time path

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Hi @kimjaewon,

>>Why is the Hold time path delay more shorter than the Setup time path delay?

As per my knoweldge, I will say Vivado router prioritizes fixing hold over setup. 

This is because your design may work in the lab if you are failing setup by a small amount. There is always the option of lowering the clock frequency. If you have hold violations, the design will most likely not work.

For more info. Check UG 906 : page 268, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug906-vivado-design-analysis.pdf

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
6 Replies
Moderator
Moderator
595 Views
Registered: ‎03-16-2017

Re: Hold time path vs Setup time path

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Hi @kimjaewon,

>>Why is the Hold time path delay more shorter than the Setup time path delay?

As per my knoweldge, I will say Vivado router prioritizes fixing hold over setup. 

This is because your design may work in the lab if you are failing setup by a small amount. There is always the option of lowering the clock frequency. If you have hold violations, the design will most likely not work.

For more info. Check UG 906 : page 268, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug906-vivado-design-analysis.pdf

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Adventurer
Adventurer
584 Views
Registered: ‎11-18-2017

Re: Hold time path vs Setup time path

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Thanks for your help.

What does work in the lab means?

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Moderator
Moderator
581 Views
Registered: ‎03-16-2017

Re: Hold time path vs Setup time path

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Hi @kimjaewon,

 

It means downloading your bitstream on fpga. Checking functionality of your code on board. 

So, for desired functionality and to overcome any metastability on FPGA board hold fix is on first priority.

Regards,
hemangd

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Highlighted
Adventurer
Adventurer
578 Views
Registered: ‎11-18-2017

Re: Hold time path vs Setup time path

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Thanks very much.

I have one last question.

Why is the requirement of hold time is 0 ns?

I understand that requirement of setup time is 10 ns because my clock is 10 ns.

But I can't understand why the hold time requirement is 0 ns.

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Moderator
Moderator
569 Views
Registered: ‎03-16-2017

Re: Hold time path vs Setup time path

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Hi @kimjaewon,

 

Please refer setup/recovery relationship and hold/removal relationship from UG 906. It has detailed explanation on how requirement gets calculated., page 222 to225. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug906-vivado-design-analysis.pdf

 

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Historian
Historian
493 Views
Registered: ‎01-23-2009

Re: Hold time path vs Setup time path

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Why is the Hold time path delay more shorter than the Setup time path delay?

It is not really the fact that it is a hold vs. a setup that makes the difference, it is the process corner.

All static timing checks are done at two process corners the "Slow process corner" and the "Fast process corner". If you look at your report, you can see that the Hold is as the fast process corner and the setup is at the slow process corner.

The performance (i.e. speed) of a silicon transistor is affected by a number of characteristics - notably the Process (variation from manufactured device to manufactured device) the Voltage (the core voltage driving the transistor) and Temperature (the temperature of the transistor - i.e. the temperature of the die). Collectively these are referred to as PVT.

A device (and a design) must work on all manufactured devices at any legal combination of temperature and voltage. As such, Vivado does static timing checks at the worst combination of PVT (Slow process corner) and the best combination of PVT (Fast process corner). If a check passes at both of these corners then it will work at all legal combinations of PVT.

For most paths, setup checks are worse at the slow process corner and hold checks are worst at the fast process corner. When you ask Vivado for a report on a check it reports the worst one - hence the worst setup check is shown at the slow process corner, and the worst hold at the fast. But the other checks are done as well, and with the right report_timing command you can get the tool to report the other checks as well - although one rarely cares about the process corner that does not result in the worst timing...

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