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Observer alectronic
Observer
806 Views
Registered: ‎04-14-2014

Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hello ,

 

I'm not a expert in the subject of fixing hold time violations , so I need help .

After synthesis the timing report shows me a lot of hold time violations between two generated clocks : o_CLOCK1x and o_CLOCK1x_1 .

Hold_Results after synthese.png

After a report_clock , I found that these two clocks can't run at the same time .

o_CLOCK1x is a PLL's output when the master clock is Top_Xapp1249_inst/SDI/GTX_Rx/gtxe2_i/RXOUTCLK and o_CLOCK1x_1 is the same PLL's output when the master clock is i_ANA_CLK .

At the input of this PLL , there is a MUX_CLK between these two master clocks .

Clock_Report.png

 

 

So I try the following contraint :

set_clock_groups -physically_exclusive -group o_CLK1x_1 -group o_CLK1x 

but this contraint do not reduce the total of the number of Hold failing endpoints .

I try  the following contraints too :

set_clock_groups -name Groupe_3 -physically_exclusive -group [get_clocks Top_Xapp1249_inst/SDI/GTX_Rx/gtxe2_i/RXOUTCLK] -group [get_clocks -of_objects [get_pin TOP_HDMI_SDI_ANA_inst/GESTION_CLKs_inst/PLL_SP_inst/PLLE2_BASE_inst/CLKOUT0] -filter {IS_GENERATED && MASTER_CLOCK == i_ANA_CLK}]

set_clock_groups -name Groupe_6 -physically_exclusive -group [get_clocks i_ANA_CLK] -group [get_clocks -of_objects [get_pins TOP_HDMI_SDI_ANA_inst/GESTION_CLKs_inst/PLL_SP_inst/PLLE2_BASE_inst/CLKOUT0] -filter {IS_GENERATED && MASTER_CLOCK == Top_Xapp1249_inst/SDI/GTX_Rx/gtxe2_i/RXOUTCLK}]

but these contraints do not reduce the total of the number of Hold failing endpoints .

What is the contraint I have to write to reduce this number ?

Thanks in advance

Alex

 

 

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1 Solution

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Observer alectronic
Observer
703 Views
Registered: ‎04-14-2014

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hi @watari,

Thank you for your prompt reply .

I just try this following contraint :

set_clock_groups -physically_exclusive -group [get_clocks I_3] -group [get_clocks I_2]

I do the same for the all CLKs that there is no interaction and the number of the Hold failing Endpoints falls to 46 after synthesis .

This number falls to 0 after implementation .

Good news and thanks for this support .

Regards

Alex

 

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9 Replies
Observer alectronic
Observer
793 Views
Registered: ‎04-14-2014

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hello,

I try the following and the number of total decrease from 1188 to 261 . Do you confirm that is the right contraint I have to write?

set_clock_groups -name Groupe_5 -physically_exclusive -group [get_clocks -of_objects [get_pins TOP_HDMI_SDI_ANA_inst/GESTION_CLKs_inst/PLL_SP_inst/PLLE2_BASE_inst/CLKOUT0] -filter {IS_GENERATED && MASTER_CLOCK == Top_Xapp1249_inst/SDI/GTX_Rx/gtxe2_i/RXOUTCLK}] -group [get_clocks -of_objects [get_pins TOP_HDMI_SDI_ANA_inst/GESTION_CLKs_inst/PLL_SP_inst/PLLE2_BASE_inst/CLKOUT0] -filter {IS_GENERATED && MASTER_CLOCK == i_ANA_CLK}]

Alex

 

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Scholar watari
Scholar
790 Views
Registered: ‎06-16-2013

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hi @alectronic

 

I'm not sure.

> set_clock_groups -physically_exclusive -group o_CLK1x_1 -group o_CLK1x 

But this is not correct.

Maybe here is correct description.

 

set_clock_groups -physically_exclusive -group [get_clocks o_CLK1x_1] -group [get_clocks o_CLK1x]

 

Would you try it ?

 

Best regards,

 

 

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Observer alectronic
Observer
780 Views
Registered: ‎04-14-2014

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hello,

Now I want to have a look on the hold time violations between I_3 and I_2 .

The synthesis report :

Hold_Results after synthese.png

And the clock report :

Clock_Report_2.png

 

As you can see , the master clocks is two different PLL's outputs , the PLL I spoke about in my first post .

I tried the following contraint :

set_clock_groups -name Groupe_5 -physically_exclusive -group [get_clocks -of_objects [get_pins TOP_HDMI_SDI_ANA_inst/TOP_OUTPUT_inst/top4_Tx_inst/clkgen/loop8.tx_mmcm_adv_inst/CLKIN1] -filter {IS_GENERATED && MASTER_CLOCK == o_CLK1x}] -group [get_clocks -of_objects [get_pins TOP_HDMI_SDI_ANA_inst/TOP_OUTPUT_inst/top4_Tx_inst/clkgen/loop8.tx_mmcm_adv_inst/CLKIN1] -filter {IS_GENERATED && MASTER_CLOCK == o_CLKdiv2}]

but in the TCL Console there was displayed the following warning :

WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins TOP_HDMI_SDI_ANA_inst/TOP_OUTPUT_inst/top4_Tx_inst/clkgen/loop8.tx_mmcm_adv_inst/CLKIN1] -filter {IS_GENERATED && MASTER_CLOCK == o_CLK1x}'.
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins TOP_HDMI_SDI_ANA_inst/TOP_OUTPUT_inst/top4_Tx_inst/clkgen/loop8.tx_mmcm_adv_inst/CLKIN1] -filter {IS_GENERATED && MASTER_CLOCK == o_CLKdiv2}'.
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.

How can I create these two generated clocks : o_CLCK1x  and o_CLKdiv2  coming from two differents output of a PLL?

Thanks in advance .

Alex

 

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Observer alectronic
Observer
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Registered: ‎04-14-2014

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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hi @watari,

Thanks for your reply .

I tried the last contraint you suggested me and the number of failing endpoints  is decreased  from 1188 to 261 , the same as the contraint I have suggested .

Please could you have a look on me last message regarding ""create clocks from PLL's output" ?

Thanks in advance .

Alex

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Observer alectronic
Observer
760 Views
Registered: ‎04-14-2014

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hello ,

With several '' set clock_group - physically_exclusive '' contraints , the number of failing endpoints decrease to 46 .

I can't do anything now . Right ? (There is no more clock's domain crossing)  .

Hope that there is no time violation after implementation .

Clock_Report_3.png

 

Thanks in advance .

Alex

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Scholar watari
Scholar
750 Views
Registered: ‎06-16-2013

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hi @alectronic

 

I'd like to confirm your current clock settings.

Would you share me the result of report_clocks ?

 

I think that you don't need like complex setting and you can describe more simple constraints.

 

Best regards,

 

Best regards,

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Observer alectronic
Observer
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Registered: ‎04-14-2014

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hi @watari,

Please find attached the file .

Regards

Alex

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Scholar watari
Scholar
717 Views
Registered: ‎06-16-2013

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hi @alectronic

 

Unfortunetly, Vivado does not recognize what you describe. (Refer the result of "report_clocks" command. line from 4 to 61).

It means that you can use these clock settins at get_clocks command.

 

In this case, there are two solution.

 

Solution 1)

Change location of clock setting from your description to ex. I_2.

 

Solution 2)

I'm not sure. But I suggest using get_object command instead of -of_objects.

Because of "get_clocks" command requests clock object.

 

Best regards,

 

[get_clocks [get_objects [get_pins TOP_HDMI_SDI_ANA_inst/TOP_OUTPUT_inst/top4_Tx_inst/clkgen/loop8.tx_mmcm_adv_inst/CLKIN1] -filter {IS_GENERATED && MASTER_CLOCK == o_CLK1x}]]

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Observer alectronic
Observer
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Registered: ‎04-14-2014

Re: Hold time violation around a PLL with two masters in clock that can't be run at the same time

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Hi @watari,

Thank you for your prompt reply .

I just try this following contraint :

set_clock_groups -physically_exclusive -group [get_clocks I_3] -group [get_clocks I_2]

I do the same for the all CLKs that there is no interaction and the number of the Hold failing Endpoints falls to 46 after synthesis .

This number falls to 0 after implementation .

Good news and thanks for this support .

Regards

Alex

 

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