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Visitor
Visitor
3,480 Views
Registered: ‎06-30-2017

Hold time violation between MMCM output clock and generated_clock

Hi there,

 

I am using a MMCM in my design to create a 100 MHz clock CLK1.

clk_wiz_0 inst_clk_wiz_0
  (
  // Clock out ports  
  .clk_out1(CLK1),   // 100 MHz
  .clk_out2(SYSCLK),    // 80 MHz
  // Status and control signals               
  .reset(cpu_rst),  // 
  .locked(locked),
 // Clock in ports
  .clk_in1_p(SYSCLK_P),
  .clk_in1_n(SYSCLK_N)
  );

 

I use CLK1 to create another clock as output of the module with "create_generated_clock" constraint as follows 

 

 

create_generated_clock -name g_clk_1 -source [get_pins clkf_buf/I] -divide_by 1 [get_ports GCLK]

 

where clk_buf is instantiation of BUFG (global buffer) which has CLK1 from MMCM as input.

  BUFG clkf_buf  (.O (GCLK),    .I (CLK1));

 

I use GCLK as input clock to selectiveIO where I sample output of the module to pins.

selectio_wiz_0
   // width of the data for the system
 #(.SYS_W(8),
   // width of the data for the device
   .DEV_W(8))
 inst_selectio_wiz_0(
  // From the system into the device
  .data_in_from_pins(Dout),
  .data_in_to_device(DATA}),
  .clk_in(GCLK),        // Fast clock input from PLL/MMCM
  .io_reset(p_rst));

 

The problem I find is that in timing report, I find hold time violation between input of selectIO and output of selectIO in inter-clock paths between clk_out1(MMCM CLK1 output) and GCLK. This does not make sense to me since GCLK is generated from CLK1.

I use CLK1 to drive my internal logic to present data at the input of the selectIO.

 

Can someone please explain what I am doing wrong?

 

Thanks in advance. Appreciate your time

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4 Replies
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Moderator
Moderator
3,355 Views
Registered: ‎01-16-2013

Re: Hold time violation between MMCM output clock and generated_clock

Hi,

 

The clock constraint should be on Input clock as create_clock, you need not to provide any create_generated clock on BUFG instance as it should auto-generated clock by tool.

Also after changing above constraints re-run the flow and provide us the timing report.

 

Thanks,
Yash

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Guide
Guide
3,337 Views
Registered: ‎01-23-2009

Re: Hold time violation between MMCM output clock and generated_clock

You haven't given us enough information.

 

First, you are instantiating several cores that are highly configurable and can have different clocking logic within them.

 

I am inferring that the clk_wiz core has an MMCM in it (which isn't necessarily true). However, in the default configuration, the clock wizard will instantiate BUFGs on all the outputs, so CLK1 and SYSCLK probably already have BUFGs.

 

Therefore, it is probably incorrect to instantiate a second BUFG on CLK1 to generate GCLK.

 

Furthermore, the selectIO wizard can also contain clocking resources - it can instantiate an MMCM and BUFGs, or BUFR/BUFIO combinations. I will assume that it has no internal clocking.

 

Next, there is the create_generated_clock. Why do you have this? Are you trying to forward the clock out to an output port? If so, directly connecting the internal clock to the output port is not the way to do it - you should instantiate an ODDR (in fact the SelectIO wizard can do this for you).

 

Finally, you don't tell us where the hold time violation is. If it is internal on a FF driven by CLK1 and a FF driven by GCLK, then this is correct. By instantiating a second BUFG, GCLK will be delayed with respect to CLK1 by a significant amount - as much as 3ns. This will create nasty hold time problems (which is why you shouldn't instantiate a second BUFG).

 

If the hold time is between an internal FF and the output port, then the hold time violation is related to the output constraints - you don't show us those...

 

Avrum

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Visitor
Visitor
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Registered: ‎06-30-2017

Re: Hold time violation between MMCM output clock and generated_clock


 

Therefore, it is probably incorrect to instantiate a second BUFG on CLK1 to generate GCLK.

 

 


Thanks for the explanation. I removed the unnecessary BUFG .

 


 

Next, there is the create_generated_clock. Why do you have this? Are you trying to forward the clock out to an output port? If so, directly connecting the internal clock to the output port is not the way to do it - you should instantiate an ODDR (in fact the SelectIO wizard can do this for you).

 

 


I have used a selectIO DDR instance to output the GCLK. What if I want to set constraints on some output ports and the GCLK. How can I do it? I thought I need a clock to set setup and hold time constraints. That is why I used the create_generated_clock constraint.

 

 


 

 

If the hold time is between an internal FF and the output port, then the hold time violation is related to the output constraints - you don't show us those...

 


 

The hold time is between input ports of the selectIO and the output ports.

 

 

Thanks and regards,

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Hold time violation between MMCM output clock and generated_clock

Hi,

Can you please share the setup and hold analysis report for the path which is under discussion?

Also please share the clock forwarding schematic you are using here.
Just for confirmation share the XDC constraints as well.

Thanks,
Yash
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