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Adventurer
Adventurer
4,039 Views
Registered: ‎11-09-2016

Hold violation

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Hi,

I have primary external clock(27MHz) and two internal clocks(54MHz,216MHz) generated by Clock Wizard.

The timing analysis says hold violation,slack values are 0.009ns and 0.130ns.

I didn't use ant constraint between 54MHz and 216MHz domains.

h1.png

 

Vivado can fix automatically these violations or I made a big mistake?

How can i learn,my error associated which one?(PERIOD or OFFSET IN)

Says here:verify that the design is using the global clocking resources.(How can do it?)

https://www.xilinx.com/support/answers/21367.html

 

I've read some solutions in forums, but indeed i need to help specifically. I also attached timing report.

 

Thanks

 

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Guide
Guide
5,573 Views
Registered: ‎01-23-2009

@berker_atel,

 

I disable opt_design option in implementation settings. Now,i can get slack times and hold violation fixed.

I want to ask, we can say this problem doesn't related my design? This method safe and guaranteed to work in practice?

 

Almost certainly not (on both your questions).

 

It is generally not legal to disable opt_design - I am actually surprised that the tools allowed you to proceed...

 

One of opt_design's main functions is to "clean up" your design - remove unconnected outputs, tie off and propagate unconnected inputs. Almost certainly, this is the source of your problems.

 

If you leave opt_design enabled and run full implementation, have you opened up the implemented design and looked at the schematic. From what you are reporting, it is possible that there will be nothing there... If there is some gross error in your RTL that causes the entire design to be redundant (for example, your reset is always asserted, or your clock doesn't propagate to anything or anything that causes all your outputs to be constants), then the tools will remove all the logic, leaving you with a design that has nothing but output buffers driving constants. If this is the case, then your timing constraints become meaningless - all timing is N/A because there are no timing paths.

 

So, first check to see if this is the case. If it is, then you need to do RTL simulation to make sure your design does "something" - the types of errors that cause logic to be removed like this are very obvious in simulation (basically your RTL will do nothing at all at the outputs of the FPGA).

 

Avrum

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Moderator
Moderator
4,022 Views
Registered: ‎09-15-2016

Hi @berker_atel

 

I checked the timing report you shared, as the 54 Mhz and 216 Mhz clocks coming out of MMCM are related clocks. So as per my understanding to make the requirement to be calculated correctly by tool you need to have multicycle constraints for those clocks.

The current requirement for set up for 54 Mhz and 216 Mhz clk is 4.630 ns which is wrong to my knowledge. Please  use multi cycle constraints for both setup and hold.

Please refer the below link, page 117 to know more on this and make the necessary modifications:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug903-vivado-using-constraints.pdf

 

Hope this helps.

 

Regards

Rohit

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Regards
Rohit
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Adventurer
Adventurer
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Registered: ‎11-09-2016

Thanks for your reply,

Is there any big design mistake?Or Multicycle constraints use everytime in similar conditions?

I just want to transfer a data between 54MHz and 216MHz domains.

Is path multiplier option 4 for this condition?(216/54)

Which one i have to use, startpoint to endpoint or source clock to dest clock?

 

Best Regards

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Guide
Guide
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Registered: ‎01-23-2009

So as per my understanding to make the requirement to be calculated correctly by tool you need to have multicycle constraints for those clocks.

 

I have to disagree.

 

These two clocks come out of the same MMCM and use the same buffer. They are properly constrained from the single constraint on the input clock to the FPGA.

 

The setup path requirement of 4.63ns is correct - it represents one period of the faster clock.

 

The hold requirement of 0.00ns is also correct, and the clock structure (and hence skew) look correct.

 

You do not need (and, in fact, must not have) set_multicycle_path commands on these paths.

 

So why are there hold time violations?

 

Is this report from after implementation or after synthesis? Hold times are fixed by the router, so if the design is not yet routed (implemented), it is normal to see small hold time violations (like these). You only need to worry about hold time violations after the design is fully routed.

 

If this design is already implemented (place and route), then I don't know why the tools didn't fix the hold times - it should have been able to...

 

Avrum

Adventurer
Adventurer
3,966 Views
Registered: ‎11-09-2016

Hi @avrumw

thanks for reply.

My implementation results show as NA. I checked there is crate_clock constraint. This is auto generated by Clock Wizard. I didn't write manually. When i say,report timing, Vivado warn me as "timing results are empty".

I searched this, people say: missing constraint. But I have a create clock and a input delay constraints at least. 

How can i solve this problem?

 

Best Regards

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Adventurer
Adventurer
3,932 Views
Registered: ‎11-09-2016

I disable opt_design option in implementation settings. Now,i can get slack times and hold violation fixed.

I want to ask, we can say this problem doesn't related my design? This method safe and guaranteed to work in practice?

 

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Guide
Guide
5,574 Views
Registered: ‎01-23-2009

@berker_atel,

 

I disable opt_design option in implementation settings. Now,i can get slack times and hold violation fixed.

I want to ask, we can say this problem doesn't related my design? This method safe and guaranteed to work in practice?

 

Almost certainly not (on both your questions).

 

It is generally not legal to disable opt_design - I am actually surprised that the tools allowed you to proceed...

 

One of opt_design's main functions is to "clean up" your design - remove unconnected outputs, tie off and propagate unconnected inputs. Almost certainly, this is the source of your problems.

 

If you leave opt_design enabled and run full implementation, have you opened up the implemented design and looked at the schematic. From what you are reporting, it is possible that there will be nothing there... If there is some gross error in your RTL that causes the entire design to be redundant (for example, your reset is always asserted, or your clock doesn't propagate to anything or anything that causes all your outputs to be constants), then the tools will remove all the logic, leaving you with a design that has nothing but output buffers driving constants. If this is the case, then your timing constraints become meaningless - all timing is N/A because there are no timing paths.

 

So, first check to see if this is the case. If it is, then you need to do RTL simulation to make sure your design does "something" - the types of errors that cause logic to be removed like this are very obvious in simulation (basically your RTL will do nothing at all at the outputs of the FPGA).

 

Avrum

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Adventurer
Adventurer
3,904 Views
Registered: ‎11-09-2016

Hi @avrumw

 

"basically your RTL will do nothing at all at the outputs of the FPGA" .

Yes, you're absolulety right. I have 2 blocks, Output of first block connected to input of second block.There is a top level output of design from second block's output. First block doing real something(like interpolation..), second block only read result of interpolation(but doesn't interpret interpolation value or doesn't give output related with interpolation value) and give a dummy output(this goes to fpga output pin). So maybe vivado thinks that regardless of input, output is constant like you say exactly.

I replaced second block real and logical one, the timings are good now. Also Router fixed the hold time violation problem. I have to trust router because i believe the source of the problem doesn't related design now.

I learn a lot of thing with doing mistake, was very useful.

Thanks

Best regards

 

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