We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer premnath
Registered: ‎11-12-2018

Hold violation

Hi all,

I'm getting Hold Violation/Negative Delay/Slack for Hold path after adding Chipscope file(cdc) for my design and I also got violation warning for signal related to my design but those are not negative around 50ns. So can I ignore this violation as it is related to chipscope or How I can come out of it?

Even after this bitstream is generating properly and at the 9th Phase of Place and Route Hold is coming zero.

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (SLICE_X46Y146.SR), 1 path

 Delay (hold path):      -2.741ns (datapath - clock path skew - uncertainty) 
   Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD (FF) 
   Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH) 
   Data Path Delay:      0.757ns (Levels of Logic = 0) 
   Clock Path Skew:      3.279ns (2.175 - -1.104) 
   Source Clock:         clk_50mhz rising at 0.000ns 
   Destination Clock:    icon_control0<13> falling 
   Clock Uncertainty:    0.219ns 
   Clock Uncertainty:          0.219ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE 
     Total System Jitter (TSJ):  0.070ns 
     Discrete Jitter (DJ):       0.183ns 
     Phase Error (PE):           0.120ns 
   Minimum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     SLICE_X43Y147.AQ     Tcko                  0.216   U_ila_pro_0/U0/I_NO_D.U_ILA/iARM 
     SLICE_X46Y146.SR     net (fanout=10)       0.433   U_ila_pro_0/U0/I_NO_D.U_ILA/iARM 
     SLICE_X46Y146.CLK    Tremck      (-Th)    -0.108   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL 
     -------------------------------------------------  --------------------------- 
     Total                                      0.757ns (0.324ns logic, 0.433ns route) 
                                                        (42.8% logic, 57.2% route) 


0 Kudos
1 Reply
Registered: ‎07-18-2018

Re: Hold violation


You can't ingore this hold error if when you build the design and after implemention finishes, it still exists, because this path isn't going to function as intended.

Usually if a chipscope has issues with timing, the easyiest thing is to either sample fewer signals, or to slow the design down for the chipscope debugging.

I am not exaclty sure what this path should look like.

Could you provide a diagram of the SRC and DST FF's and Clocks, of whatever the path is, and then show where you are trying to insert the chipscope to measure it.

It might help understand what the paths in the report are covering.


0 Kudos