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273 Views
Registered: ‎03-26-2019

Hold violations

Hi,

Is it normal/common to see lot of hold violations in very small/ simple designs (8 bit adder) after synthesis, which are not there after implementation (same design and constraints) ?

Thanks and best regards

Bhawandeep Singh

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2 Replies
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: Hold violations

Hi @bhawandeep_singh ,

Post-synthesis timing report cannot be reilied on for timing closure analysis, as  accurate net delays are not avaiable at post synthesis phase. In general, do not worry about hold time violations, especially only after synthesis. Proceed to implement the design and check the timing there.

Thanks,

Raj

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Guide
Guide
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Registered: ‎01-23-2009

Re: Hold violations

To add a little more clarity, hold time violations are fixed during the route stage of implementation - any path that is too short will be lengthened by the router by adding additional routing delay. As a result, minor hold time violations after synthesis are normal and expected - they will be fixed by the router.

However, this is only true of minor hold violations (around 100ps or less) - anything larger than that is probably the result of some incorrect clocking, and should be fixed functionally - the router may not succeed at fixing larger ones, and even if it does, this has the potential to cause congestion issues due to the large amount of extra routing resources used to fix the hold violation.

Avrum