cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
7,045 Views
Registered: ‎06-18-2009

How can I count in the signal delay caused by FPGA's package when I do length matching?

           I want to implement  a DDR2 controller using Virtex-5 FPGA . When I do length matching, how can I count in the signal delay caused by FPGA's package.

Or how can I get the clk to pad delay for each I/O signals? 

           Thanks! 

0 Kudos
4 Replies
Highlighted
Explorer
Explorer
7,038 Views
Registered: ‎09-11-2007

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
7,027 Views
Registered: ‎08-13-2007

Other options include partgen, ADEPT, and PlanAhead:

http://www.xilinx.com/support/answers/22814.htm (8.1 Timing Virtex-II Pro/Virtex-4 - How do I calculate the flight time for my device?)

http://mysite.verizon.net/jimwu88/adept/

 

bt

 

== edit

Fixed ADEPT link to its new location

Message Edited by timpe on 06-19-2009 08:04 AM
0 Kudos
Visitor
Visitor
7,003 Views
Registered: ‎06-18-2009

Thanks!
0 Kudos
Highlighted
Visitor
Visitor
6,890 Views
Registered: ‎06-18-2009

1.Timing analyzer --> clock to pad delay

2.package length,  6~7.1ps/mm  

Which of the two ways above is more accuracy? 

 

0 Kudos