01-07-2013 06:23 AM
I'm trying to put a constraint on clock region (smth like AREA_GROUP “groupname” RANGE=CLOCKREGION_X#Y#;), but I don't know how they are numbered phisically on chip and I don't know what to put instead of X#Y#. In UG362 there is only information how many clock regions are in given chip. I tried to check in FPGA editor, but clock regions are divided into coloured fields - I can't find any numbers.
01-07-2013 06:34 AM
The clock region names are visible (or can be made visible) in the Vivado Device View window (and I am pretty sure in PlanAhead as well).
The numbering is pretty simple, though. The bottom left one is named CLOCKREGION_X0Y0. As you move up, the Y increases (so CLOCKREGION_X0Y1, then CLOCKREGION_X0Y2, ...). The right side clock regions are X1, so the bottom right one is CLOCKREGION_X1Y0. There are always only 2 regions left/right (so the left half are X0 and the right half are X1), and then the Y axis increases to 1/2 the number of regions - so in a device with 18 regions, the top right is CLOCKREGION_X1Y8.
01-21-2013 09:20 AM
additionally the avrumn stated, i would like to add how the region how it is spread.
clockregion_x0y0: clockregion_x0y7 then it create a rectangle
clockregion_x0y0, clockregion_x0y7 then it create a list of region