How do I configure PLL dynamic phase shifting using xilinx ISE?

[krishnachandrasekhar100]

Hi everyone,

I have to 'configure PLL dynamic phase shifting using xilinx ISE' as part of my work. But what does 'configuring PLL dynamic phase shifting using Xilinx ISE' mean? Can anyone please elaborate?

Thanks in advance

-Chandrasekhar DVS

[hongh · Accepted solution]

Hi, @krishnachandrasekhar100 ,

It means you can change the frequency of PLL/MMCM's output clock while the design is still running on the board without re-programming.

You can refer to XAPP888 for the detailed information. 

[viviany]

"dynamic phase shifting" is a function of the PLL in Xilinx device.

You can first refer to the "Clocking Resources User Guide of the xilinx device that you're using.

For examle, for Virtex6 device it is UG362.

You can find the user guide on xilinx.com.

-vivian

[krishnachandrasekhar100]

Oh, Thanks hongh. I shall refer to XAPP888 and reciprocate.

[krishnachandrasekhar100]

Thanks Vivian. I would need this clocking resources user guide for the next step in my work.

[krishnachandrasekhar100]

Hi @hongh ,

I went through XAPP878 because I am dealing with Virtex-6 FPGA. It was mentioned that the eight output clocks have two configuration registers, each, that deal with divide and phase attributes. However, how exactly can I communicate with the MMCM?. I want to program the board once and send it some commands so that the the phase of the output clock changes with reference to input clock. I think this can be done either multiplexing clock outputs of different phases to the output clock or by shifting the phase of a single output clock by its resolution. How do I do that? Also what is the relevant communication protocol? 

Thanks in advance,

-Chandrasekhar DVS

[viviany]

Have you read "Dynamic Phase Shift Interface" section in UG362?

-vivian

[krishnachandrasekhar100]

Hi @viviany 

Sorry for the late reply. I went through the 'Dynamic Phase Shift Interface' section. The PSEN,PSINCDEC,PSCLK and PSDONE signals do help in changing the phase shift of output clock.

Now, I want to use the mmcm_drp instance provided in xapp878.zip reference design to have effectively, two clock signals; input clock signal and output phase shifted clock signal(both equal in frequency) and observe the simulation. I modified the 'mmcm_drp.v' to have only CLKOUT0, removed all declarations and statements pertaining to other CLKOUTs. Changed the value of 'USE_FINE_PS' from "FALSE" to "TRUE" in top.v.

The attachments consist of the modifed 'top.v' and 'mmcm_drp.v' files.

Thanks in advance

-Chandrasekhar DVS

[krishnachandrasekhar100]

Hi @hongh 

The thing you said about 'change the frequency of PLL/MMCM's output clock while the design is still running on the board without re-programming' (let's also say we can change the phase also), can we call it partial reconfiguration?

-Chandrasekhar DVS

[krishnachandrasekhar100]

Hi @viviany ,

The dynamic phase shift interafce gives me a resolution of (1/56)th of VCO time period(T_VCO) but common control on all the clocks. Dynamic Reconfiguration Port(DRP) gives a resolution of (1/8)th of VCO time period(T_VCO) for phase shift but independant control on all the clock outputs. Is it possible to achieve resolution of (1/56)th of T_VCO and independant control on clock outputs? 

Thanks in advance

-Chandrasekhar DVS

[viviany]

Dynamic Reconfiguration is not Partial Reconfiguration.

Those are totally different functions.

For details about the PLL Dynamic Reconfiguration usage, please post the question on the following board:

https://forums.xilinx.com/t5/Other-FPGA-Architectures/bd-p/7Series

-vivian

[hongh]

Hi, @krishnachandrasekhar100 ,

In the 7 Series device and the older device, PLL/MMCM can not be included in the dynamic region, so you can not use partial reconfiguration flow to modify the frequency of PLL/MMCM.