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Voyager
Voyager
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Registered: ‎10-12-2016

How many max MMCM's driven by single port ?

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Hi friends, 

We are using VCU118. 

In my design, we have 4 MMCM's which are driven by single clock from PAD(external crystal). 

1) How many max MMCM's driven by single port ?

Any help or suggestions are highly appreciated. 

-Sam

-Sampath
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Guide
Guide
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Registered: ‎01-23-2009

The "normal" answer is one.

The only "direct" input to the CLKIN of an MMCM are the clock capable pins in the same clock region/IObank as the MMCM. Since there is only one MMCM in each clock region, a given clock capable pin can only directly drive the input to that MMCM. Anything else needs to use some "non-dedicated" routing.

The second set of connections to an MMCM use the "clock backbone". These need to be enabled using the property

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets <from_IBUF_to_MMCM>]

(In UltraScale/UltraScale+ you can also use SAME_CMT_COLUMN instead of BACKBONE)

Using the backbone, a clock capable I/O can drive any MMCM input in the same I/O column on the same SLR as the clock input. The VU9P device (which is on the VCU118) has 3 SLRs, each of which is 5 clock regions high. Therefore, a clock capable pin in any one of the SLRs can reach the MMCMs in the 5 I/O banks in the same column of the same SLR - so with the BACKBONE you can reach 5 MMCMs.

However, it is worth noting that the insertion delay to the MMCMs that are not in the same I/O bank/clock region as the clock capable pin will be larger (and uncompensated) than the one to the MMCM in the same clock region.

Next (UltraScale/UltraScale+ only) you can tell the tool to use global routing to get to the MMCMs

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets <from_IBUF_to_MMCM>]

This lets the tool use a global route to get to the MMCMs. This will also have long and uncompensated insertion delay all the MMCMs. However, at least it will be fixed from route to route. It will also likely have higher clock jitter since the clock is passing throug the core. Of course, this uses one of the global clock networks in the device, but there are lots of them in US/US+.

Finally, you can reach the input of an MMCM from "general fabric" if the CLOCK_DEDICATE_ROUTE is set to FALSE

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <from_IBUF_to_MMCM>]

Now the route can take any path needed, and hence can reach all the MMCMs in the device. But, this route can go pretty much anywhere on the die, and in addition to the long and uncompensated insertion delay, will also have insertion delay that can vary from run to run, and significantly increased jitter on the clocks.

But the next question is - why would you need to drive multiple MMCMs with the same clock input. Each MMCM can generate 6 (or 7 if you use the CLKFBOUT) different clocks - using 4 MMCMs would be able to generate something like 25 clocks. Why would you need 25 different clocks all derived from the same source? What are you using the clocks for? Almost certainly there is a better way of accomplishing what you need without having 25 different clocks!

Avrum

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4 Replies
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Guide
Guide
471 Views
Registered: ‎01-23-2009

The "normal" answer is one.

The only "direct" input to the CLKIN of an MMCM are the clock capable pins in the same clock region/IObank as the MMCM. Since there is only one MMCM in each clock region, a given clock capable pin can only directly drive the input to that MMCM. Anything else needs to use some "non-dedicated" routing.

The second set of connections to an MMCM use the "clock backbone". These need to be enabled using the property

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets <from_IBUF_to_MMCM>]

(In UltraScale/UltraScale+ you can also use SAME_CMT_COLUMN instead of BACKBONE)

Using the backbone, a clock capable I/O can drive any MMCM input in the same I/O column on the same SLR as the clock input. The VU9P device (which is on the VCU118) has 3 SLRs, each of which is 5 clock regions high. Therefore, a clock capable pin in any one of the SLRs can reach the MMCMs in the 5 I/O banks in the same column of the same SLR - so with the BACKBONE you can reach 5 MMCMs.

However, it is worth noting that the insertion delay to the MMCMs that are not in the same I/O bank/clock region as the clock capable pin will be larger (and uncompensated) than the one to the MMCM in the same clock region.

Next (UltraScale/UltraScale+ only) you can tell the tool to use global routing to get to the MMCMs

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets <from_IBUF_to_MMCM>]

This lets the tool use a global route to get to the MMCMs. This will also have long and uncompensated insertion delay all the MMCMs. However, at least it will be fixed from route to route. It will also likely have higher clock jitter since the clock is passing throug the core. Of course, this uses one of the global clock networks in the device, but there are lots of them in US/US+.

Finally, you can reach the input of an MMCM from "general fabric" if the CLOCK_DEDICATE_ROUTE is set to FALSE

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <from_IBUF_to_MMCM>]

Now the route can take any path needed, and hence can reach all the MMCMs in the device. But, this route can go pretty much anywhere on the die, and in addition to the long and uncompensated insertion delay, will also have insertion delay that can vary from run to run, and significantly increased jitter on the clocks.

But the next question is - why would you need to drive multiple MMCMs with the same clock input. Each MMCM can generate 6 (or 7 if you use the CLKFBOUT) different clocks - using 4 MMCMs would be able to generate something like 25 clocks. Why would you need 25 different clocks all derived from the same source? What are you using the clocks for? Almost certainly there is a better way of accomplishing what you need without having 25 different clocks!

Avrum

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Voyager
Voyager
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Registered: ‎10-12-2016

Hi @avrumw , 

Thank you so much for your patiency. 

Actually i need around 15 clocks, as it is not possible from the top we are generating from the MMCM. 

Pls suggest me some references to get good grip on clock resource and better ways for clocks generation and routing. 

-Sam

 

-Sampath
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Guide
Guide
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Registered: ‎01-23-2009

The only resource I can suggest is the Clocking User Guide for the family you are using - so UG571 for UltraScale/UltraScale+ and UG472 for the 7 series.

Avrum

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Voyager
Voyager
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Registered: ‎10-12-2016
Thank you @avrunmw.
-Sampath
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