How much the hold slack should be in normal case?

[buddha1987]

I have a design that some of logic is driven and captured by the 150Mhz clock. I found most of these logic has the hold slack that is low than 0.1 ns (the minimum is 0.03 ns). Although the timing is closed, wil these hold slack be enough to ensure the system is stable? As I know it seems usually the hold slack is smaller than setup slack, but how much it should be to ensure a stable system in normal case ?

Thanks.

[viviany]

Is your hold slack positive or negative? Hold slack should be at least 0 (positive) to ensure the design is stable.

[buddha1987]

Hello viviany,
All the slacks inside my design are postive. So that is why I said my timing is closed.

I may ask my question in another way, does the all slacks are positive mean the stable system without timing issue no matter how small the minimum slack is ?

Thanks.

[viviany · Accepted solution]

Yes, as long as your design is correctly constrained.

When the slack is a small positive value, you may consider that a system jitter or input jitter need to be added to take the noise from board into account. In general, you can try to add 200-300ps system jitter. As for the input jitter, you can refer to the data sheet of the crystal oscillator on your board.

[buddha1987]

Thanks, viviany.

Should I add the jitter in the "create_clock" command?

[buddha1987]

It seems there is no option in the command "create_clock" that add the jitter. How should I add the jitter? Change the clock period with plus or minus 200-300ps?

Thanks.

[avrumw]

You use the "set_input_jitter" command to set the jitter on a clock

set_input_jitter  [-quiet] [-verbose] <clock> <input_jitter>

The <clock> can be the name of the clock (which was created with the create_clock command), or you can use the get_clocks command. The <input_jitter> is specified in NANOSECONDS (not picoseconds as it was with ISE).

Avrum

[buddha1987]

Thanks very much, Avrum.