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Observer swseo83
Observer
296 Views
Registered: ‎05-23-2017

How to align the phase of the output clock which is generated by MMCM to input clock.

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How can I align the phase of the output clock generated by MMCM to input clock.

 

Please take a look at the attached figure.

clk_usb is input clock in the FPGA, and clk_main is output clock generated by MMCM.

We set "Phase Alignment", when it is generated, but, as you can see,

The propagation delay for input to output is about 0.24 ns. This is critical for our project.

 

Please help us solve this problem.

 

Thank you very much.

MatchingMMCMClockingPhase.jpg
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Historian
Historian
231 Views
Registered: ‎01-23-2009

Re: How to align the phase of the output clock which is generated by MMCM to input clock.

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I don't know what you are trying to accomplish here, and I don't know what you are measuring.

If a 0.24ns delay is "critical for your project" then you have a BIG problem. Nothing in an FPGA (or ASIC) can ever be guaranteed to have an "exact" delay. All digital logic has variation. Even the best PLL cannot phase match to exactly 0, there is always some phase error. And if you are going through any logic at all, then the variation in that logic is going to have far more variability than 240ps.

So, whatever you are doing, you need to take a step back. If you are doing anything "normal" than a delay of 0.24 (or even quite a bit more significant than this) is harmless, expected, and fully dealt with in a synchronous design flow. If a delay like this is "critical" to your design, then either there is something you don't understand about how digital systems normally operate or you are doing something very unusual, and something that is probably either impossible or at least VERY complicated to accomplish in an FPGA.

Avrum

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2 Replies
Scholar watari
Scholar
250 Views
Registered: ‎06-16-2013

Re: How to align the phase of the output clock which is generated by MMCM to input clock.

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Hi @swseo83

 

I'm not familiar with Clocking Wizard IP.

But I guess, this flow is helpful for you.

 

1. Click MMCM settins tab on Clocking Wizard IP

2. Check Allow Override Mode

3. Set 0.24[ns] on CLKFBOUT_PHASE

4. You can generate phase shifted clock on MMCM.

 

Best regards,

 

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Historian
Historian
232 Views
Registered: ‎01-23-2009

Re: How to align the phase of the output clock which is generated by MMCM to input clock.

Jump to solution

I don't know what you are trying to accomplish here, and I don't know what you are measuring.

If a 0.24ns delay is "critical for your project" then you have a BIG problem. Nothing in an FPGA (or ASIC) can ever be guaranteed to have an "exact" delay. All digital logic has variation. Even the best PLL cannot phase match to exactly 0, there is always some phase error. And if you are going through any logic at all, then the variation in that logic is going to have far more variability than 240ps.

So, whatever you are doing, you need to take a step back. If you are doing anything "normal" than a delay of 0.24 (or even quite a bit more significant than this) is harmless, expected, and fully dealt with in a synchronous design flow. If a delay like this is "critical" to your design, then either there is something you don't understand about how digital systems normally operate or you are doing something very unusual, and something that is probably either impossible or at least VERY complicated to accomplish in an FPGA.

Avrum

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