02-08-2009 10:19 AM
I have XPS 10.1 and I did not edit my ucf before.
I have an NPI based peripheral connected to the mpmc.
I must connect the NPI_clk to the 125 MHz clock.
so I edited my MHS
/////////////// clock_generator ////////////
PORT CLKOUT1 = DDR2_SDRAM_mpmc_clk_s
/////////////////// mpmc ///////////////////
PORT MPMC_Clk0 = DDR2_SDRAM_mpmc_clk_s
///////////////// MY_NPI_Peripheral //////////////////
PORT NPI_clk = DDR2_SDRAM_mpmc_clk_s
When I synthesise the system, generate a report, i find the NPI_clk has a max of 104 MHz only!
How do I add a timing constraint to fix this issue?
My peripheral does not operate on real FPGA, data seems to be corrupted.
Thanks in advance,
02-11-2009 01:25 PM - edited 02-11-2009 01:26 PM
when you connected NPI_clk to DDR2_SDRAM_mpmc_clk_s, you automatically constrained it, because there is a PERIOD constraint attached to the DDR2_SDRAM_mpmc_clk_s.
I think you should try to optimize your peripheral.
Maybe add more pipeline stages before the NPI port or something.
02-18-2009 07:58 PM
You could create a new timing group, only including the NPI_clk, then apply a new PERIOD constraint to that group, and it will overwrite the original one.
You may tighten the constraint value.