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Anonymous
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How to apply a constraint MY_Peripheral_clk_in from DCM_out_clk

Hello all,

 

I have XPS 10.1 and I did not edit my ucf before.

I have an NPI based peripheral connected to the mpmc.

 

I must connect the NPI_clk to the 125 MHz clock.

 

 so I edited my MHS

 

 /////////////// clock_generator ////////////

PORT CLKOUT1 = DDR2_SDRAM_mpmc_clk_s 

 

/////////////////// mpmc ///////////////////

 PORT MPMC_Clk0 = DDR2_SDRAM_mpmc_clk_s

 

///////////////// MY_NPI_Peripheral //////////////////

 PORT NPI_clk = DDR2_SDRAM_mpmc_clk_s

 

When I synthesise the system, generate a report, i find the NPI_clk has a max of 104 MHz only!

 How do I add a timing constraint to fix this issue?

My peripheral does not operate on real FPGA, data seems to be corrupted.

 

Thanks in advance,

Tarek

 

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Contributor
Contributor
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Registered: ‎09-10-2008

Hi Tarek,

 

when you connected NPI_clk to  DDR2_SDRAM_mpmc_clk_s, you automatically constrained it, because there is a PERIOD constraint attached to the DDR2_SDRAM_mpmc_clk_s.

 

I think you should try to optimize your peripheral.

Maybe add more pipeline stages before the NPI port or something.

Message Edited by ivan.mironenko on 11-02-2009 10:26 PM
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Anonymous
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You could create a new timing group, only including the NPI_clk, then apply a new PERIOD constraint to that group, and it will overwrite the original one.

You may tighten the constraint value.

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Anonymous
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Can you specify how to do this?

 

I'm stuck in this issue for two weeks now.

 

Thanks in advance,

Tarek 

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