cancel
Showing results for
Did you mean:
Highlighted
Visitor
2,371 Views
Registered: ‎11-02-2017

## How to calculate the Clock Period?

Dear All,

I implemented a 32-bit adder by targeting a Kintex-7 FPGA by making use of the fast carry logic inherent in the FPGA. a31 to a0, and b31 to b0 are the inputs, and s32 to s0 are the sum outputs. I have attached the Verilog code and the post-place and route static timing report. May I know how to determine the minimum clock period from this report? BTW, does the clock to destination pad delay given in the second table refers to the combinational path delays for the different sum outputs? I would greatly appreciate your early reply.

Bala

1 Solution

Accepted Solutions
Highlighted
Visitor
3,108 Views
Registered: ‎11-02-2017

## Re: How to calculate the Clock Period?

Thank you Avrum for your admonishing. I am new to the forum and I think I panickedly push the buttons! Anyways, thank you for your suggestion and inputs.

3 Replies
Highlighted
Teacher
2,358 Views
Registered: ‎07-09-2009

## Re: How to calculate the Clock Period?

A good question,

but not one that can be answered as such, due to the way the tools work,

a) The tools place and route to meet your time constraints,

they won't start to optimise till you push

b)  the IO of a device are much slower than the internal logic, so if your routing to the io, the design will be slower than internal only.

c) design optimization,  in the real design, using multiple of these and other parts, the optimiser can do just that , and speed stuff up.

Highlighted
Guide
2,340 Views
Registered: ‎01-23-2009

## Re: How to calculate the Clock Period?

The speed of a design is highly dependent on a lot of factors - the complexity of the design, how it connects to other things, how the inputs and outputs are timed, the placement, the routing, the tool options, (and more).

Your design only defines one of these - the adder itself. By having the adder driven directly from inputs, at best what you can get is some information about the performance of the input pins, which is not the question you are asking (or at least not what you are really interested in).

If you are really asking "How fast can I do the 'fastest' 32 bit adder in an FPGA", the short answer is "very fast" - probably close to 500MHz. But that would only be true if

- the inputs of the adder came from flip-flops

- the output of the adder goes directly to flip-flops

- the tool is free to place these flip-flops exactly where they need to be

- not influenced by what is driving the input flip-flops

-coming from input pads will draw them toward the pins of the device

- not influenced by where the output flip-flops are driving

- going to output pads will draw them toward the outputs of the device

- you do not have a congested or overly full device

- (and many many other factors)

If you really wanted to verify this you would have to add lots more to your design to make sure the FF->FF path is unaffected by the ports - many levels of pipelining or using out-of-context builds. You would also have to write proper timing constraints, and you would have to do a complete place and route run.

But in the end, the answer is going to be "really fast". But I don't know how useful this information is going to be - this is a super simple design, and will not be indicative of any "real" design. The only meaningful questions that one has to answer are:

- how fast do I need it to be

- how can I design it to make it that fast

- how can I get the tools to help me get it there

Avrum

Highlighted
Visitor
3,109 Views
Registered: ‎11-02-2017