cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
1,648 Views
Registered: ‎08-28-2017

How to check Setup and hold time for each control signal in a design

Hi Folks,

 

I made design for zynq 7020-clg400 -2 grade.

 

I am interfacing zynq and FX3.

 

I need to check my FPGA boundary conditions.

 

How check each control signal setup and hold time?

 

Please suggest me regarding this.

 

Thanks and Best Regards

Vinod Sajjan

0 Kudos
4 Replies
Highlighted
Moderator
Moderator
1,640 Views
Registered: ‎09-15-2016

Hi @vinod.sajjan

 

I am assuming you are using Vivado. In that case, you must have written set output delay constraint to define a setup and hold relationship of your control/data signals w.r.t clock. You can open the report timing summary after implementation and  under timing tab click on check timing section. There you will see no_output_delay section which shows all the output ports without set_output_delay constraint.

Seeing this you can make it whether these ports actually need the set_output_delay contraint or not. Any voilations corresponding to the the ports having set_output_delay constraint  can be seen in the report timing summary as well.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

0 Kudos
Highlighted
Contributor
Contributor
1,629 Views
Registered: ‎08-28-2017

Hi @thakurr,

 

Thank you for replay.

 

please suggest me .

how to change setup and hold time here ?

 

Thanks and Best Regards

Vinod Sajjan

 

0 Kudos
Highlighted
Moderator
Moderator
1,626 Views
Registered: ‎09-15-2016

Hi @vinod.sajjan

 

I am not sure about your requirement here. Are you facing any set up and hold voilations here hence you want to mitigate it?

You need to share more details about the issue? If there are voilations you need to share the timing reports of the voilating paths.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

0 Kudos
Highlighted
Contributor
Contributor
1,605 Views
Registered: ‎08-28-2017

Hi @thakurr,

 

Thank you for support and time.

 

I attaching my timing report here.

 

my requirement is I need to set FPGA boundary conditions for interfacing FPGA to FX3.

for FX3 has 2ns setup and hold time for that I need to tune FPGA control signals setup and hold to more than 2ns and bit more.

 

Thanks and Best Regards

Vinod Sajjan

0 Kudos