cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
8,655 Views
Registered: ‎06-15-2015

How to constrain skews on internal signals

I need to constrain the time skew of a bus relative to a control signal, so that I can minimize the delay to latch the bus. I am using ISE14.7. Thanks for your help.

 

0 Kudos
3 Replies
htsvn
Xilinx Employee
Xilinx Employee
8,645 Views
Registered: ‎08-02-2007

hi,

 

you can apply a maxskew constraint on a net. refer to this AR. http://www.xilinx.com/support/answers/40773.html

 

this will help to understand how this maxskew is analyzed

 

--hs

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
avrumw
Guide
Guide
8,632 Views
Registered: ‎01-23-2009

There is no way of constraining skew between different signals - either in ISE or in Vivado. The "MAXSKEW" constraint in ISE simply limits the skew on a net between the different endpoints of that one net (and doesn't really work/isn't recommended anyway).

 

The only way to limit skew between signals is to limit the delay. The skew is then constrained to be between 0 (or slightly more than 0) and the maximum delay you specify.

 

In ISE this can be done on a net using the MAXDELAY constraint, or can be done on the path using a FROM TO constraint (the FROM TO is probably the preferred mechanism).

 

That being said, there are very few reasons for doing this. The only "real" one that I can think of is in a clock crossing circuit, where the skew does need to be constrained for the crosser to function properly.

 

Avrum

0 Kudos
8,629 Views
Registered: ‎06-15-2015

The situation is the data will cross from a clock domain to another. There is a data valid signal generated at the first clock domain. If the skews of the data bus signals together with the data valid signal are small enough, then the delay to latch the data at the second clock domain will minimized. 

0 Kudos