06-15-2015 01:42 PM
I need to constrain the time skew of a bus relative to a control signal, so that I can minimize the delay to latch the bus. I am using ISE14.7. Thanks for your help.
06-15-2015 06:48 PM
you can apply a maxskew constraint on a net. refer to this AR. http://www.xilinx.com/support/answers/40773.html
this will help to understand how this maxskew is analyzed
06-16-2015 06:37 AM
There is no way of constraining skew between different signals - either in ISE or in Vivado. The "MAXSKEW" constraint in ISE simply limits the skew on a net between the different endpoints of that one net (and doesn't really work/isn't recommended anyway).
The only way to limit skew between signals is to limit the delay. The skew is then constrained to be between 0 (or slightly more than 0) and the maximum delay you specify.
In ISE this can be done on a net using the MAXDELAY constraint, or can be done on the path using a FROM TO constraint (the FROM TO is probably the preferred mechanism).
That being said, there are very few reasons for doing this. The only "real" one that I can think of is in a clock crossing circuit, where the skew does need to be constrained for the crosser to function properly.
06-16-2015 06:56 AM
The situation is the data will cross from a clock domain to another. There is a data valid signal generated at the first clock domain. If the skews of the data bus signals together with the data valid signal are small enough, then the delay to latch the data at the second clock domain will minimized.