cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
wudpeker
Visitor
Visitor
5,668 Views
Registered: ‎11-03-2012

How to constrain system synchronous DDR output with different latch edge?

Jump to solution

Consider a system synchronous DDR output example like this:

 

pic001.png

There are two types of launch-latch edge relationship:

(1)

pic002.png

(2)

pic003.png

 

My question is, how to constrain them rightly in Vivado XDC? Thanks!

 

0 Kudos
1 Solution

Accepted Solutions
avrumw
Guide
Guide
9,618 Views
Registered: ‎01-23-2009

The answer is (obliquely) in the answer record - the way to alter the launch/latch edge relationship is with the set_multicycle_path command.

 

A good place to start is this post on constraining source synchronous input DDR interfaces.  The concepts are the same - we need to keep track of the four default setup checks, potentially move them forward using the set_multicycle_path command, and disable the checks that are incorrect, and then do the same thing for the hold checks.

 

So, start with the clocks:

 

create_clock -name fpga_clk -period 10 [get_ports fpga_clk_pin]

create_clock -name virt_clk -period 10

 

Like in the referenced post, the two clocks have the same timing, so they are the same clock.

 

Now define the set_output_delay commands - all 4 of them - lets say the output device needs 2ns of setup and 0.5ns of hold.

 

set_output_delay -clock virt_clk 2 [get_ports data_out]

set_output_delay -clock virt_clk -0.5 -min [get_ports data_out]

set_output_delay -clock virt_clk 2 [get_ports data_out] -clock_fall -add_delay

set_output_delay -clock virt_clk -0.5 -min [get_ports data_out] -clock_fall -add_delay

 

So, for setup we have two launch edges (rising edge internal and falling edge internal) and two capture edges (rising edge external FF, falling edge external FF), and 4 timing checks

 

a) from rising edge internal FF at 0ns to falling edge external FF at 5ns

b) from falling edge internal FF at 5ns to rising edge external FF at 10ns

c) from rising edge internal FF at 0ns to rising edge external FF at 10ns

d) from falling edge internal FF at 5ns to falling edge external FF at 15ns

 

Clearly if  a) and b) pass, then c) and d) do as well.

 

In your situation, though, you want to keep c) and d), but not a) and b), so this is done with the set_false_path command

 

set_false_path -setup -rise_from [get_clocks fpga_clk] -fall_to [get_clock virt_clk]; # diable a)

set_false_path -setup -fall_from [get_clocks fpga_clk] -rise_to [get_clock virt_clk]; # diable b)

 

The hold checks, though, are more complicated. If we look at the original system, each of the four setup checks led to a hold check

a) rising edge at 0 to falling edge at -5

b) falling edge at 5 to rising edge t 0

c) rising edge at 0 to falling edge at 0

d) falling edge at 5 to rising edge at 5

 

None of these are the correct ones for the system you are trying to describe - they are too lenient; for this system to work, the hold checks must be done to the edge before (1/2 clock cycle) the setup capture edges. So these are:

 

e) rising edge at 0 to falling edge at 5

f) falling edge at 5 to rising edge at 10

 

So now we need a set_multicycle_path - we need to push the hold checks forward. I think it's

 

set_multicycle_path -1 -hold -from [get_clocks fpga_clk] -to [get_clocks virt_clk]

 

(but I am not certain - it could be 0 instead of -1; you will have to test it to figure out which is correct)

 

So now the paths are

 

a) rising edge at 0 to falling edge at 5 (this is the correct one)

b) falling edge at 5 to rising edge t 10 (so is this)

c) rising edge at 0 to falling edge at 10

d) falling edge at 5 to rising edge at 15

 

These last two (c and d) are incorrect and will fail, and hence need to be disabled...

 

set_false_path -hold -rise_from [get_clocks fpga_clk] -rise_to [get_clock virt_clk];

set_false_path -hold -fall_from [get_clocks fpga_clk] -fall_to [get_clock virt_clk];

 

Avrum

View solution in original post

Tags (3)
4 Replies
syedz
Moderator
Moderator
5,662 Views
Registered: ‎01-16-2013

@wudpeker,

 

Check the following AR#58640

http://www.xilinx.com/support/answers/58640.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
wudpeker
Visitor
Visitor
5,640 Views
Registered: ‎11-03-2012

Hi Syed, thanks for your reply. I've seen this AR#58640 before, but I think it is talking about phase delay between launch and latch clock (same edge), not the different latch edge. Or did I miss anything? Can you please explain more details?

0 Kudos
avrumw
Guide
Guide
9,619 Views
Registered: ‎01-23-2009

The answer is (obliquely) in the answer record - the way to alter the launch/latch edge relationship is with the set_multicycle_path command.

 

A good place to start is this post on constraining source synchronous input DDR interfaces.  The concepts are the same - we need to keep track of the four default setup checks, potentially move them forward using the set_multicycle_path command, and disable the checks that are incorrect, and then do the same thing for the hold checks.

 

So, start with the clocks:

 

create_clock -name fpga_clk -period 10 [get_ports fpga_clk_pin]

create_clock -name virt_clk -period 10

 

Like in the referenced post, the two clocks have the same timing, so they are the same clock.

 

Now define the set_output_delay commands - all 4 of them - lets say the output device needs 2ns of setup and 0.5ns of hold.

 

set_output_delay -clock virt_clk 2 [get_ports data_out]

set_output_delay -clock virt_clk -0.5 -min [get_ports data_out]

set_output_delay -clock virt_clk 2 [get_ports data_out] -clock_fall -add_delay

set_output_delay -clock virt_clk -0.5 -min [get_ports data_out] -clock_fall -add_delay

 

So, for setup we have two launch edges (rising edge internal and falling edge internal) and two capture edges (rising edge external FF, falling edge external FF), and 4 timing checks

 

a) from rising edge internal FF at 0ns to falling edge external FF at 5ns

b) from falling edge internal FF at 5ns to rising edge external FF at 10ns

c) from rising edge internal FF at 0ns to rising edge external FF at 10ns

d) from falling edge internal FF at 5ns to falling edge external FF at 15ns

 

Clearly if  a) and b) pass, then c) and d) do as well.

 

In your situation, though, you want to keep c) and d), but not a) and b), so this is done with the set_false_path command

 

set_false_path -setup -rise_from [get_clocks fpga_clk] -fall_to [get_clock virt_clk]; # diable a)

set_false_path -setup -fall_from [get_clocks fpga_clk] -rise_to [get_clock virt_clk]; # diable b)

 

The hold checks, though, are more complicated. If we look at the original system, each of the four setup checks led to a hold check

a) rising edge at 0 to falling edge at -5

b) falling edge at 5 to rising edge t 0

c) rising edge at 0 to falling edge at 0

d) falling edge at 5 to rising edge at 5

 

None of these are the correct ones for the system you are trying to describe - they are too lenient; for this system to work, the hold checks must be done to the edge before (1/2 clock cycle) the setup capture edges. So these are:

 

e) rising edge at 0 to falling edge at 5

f) falling edge at 5 to rising edge at 10

 

So now we need a set_multicycle_path - we need to push the hold checks forward. I think it's

 

set_multicycle_path -1 -hold -from [get_clocks fpga_clk] -to [get_clocks virt_clk]

 

(but I am not certain - it could be 0 instead of -1; you will have to test it to figure out which is correct)

 

So now the paths are

 

a) rising edge at 0 to falling edge at 5 (this is the correct one)

b) falling edge at 5 to rising edge t 10 (so is this)

c) rising edge at 0 to falling edge at 10

d) falling edge at 5 to rising edge at 15

 

These last two (c and d) are incorrect and will fail, and hence need to be disabled...

 

set_false_path -hold -rise_from [get_clocks fpga_clk] -rise_to [get_clock virt_clk];

set_false_path -hold -fall_from [get_clocks fpga_clk] -fall_to [get_clock virt_clk];

 

Avrum

View solution in original post

Tags (3)
wudpeker
Visitor
Visitor
5,501 Views
Registered: ‎11-03-2012

Hi Avrum, thanks very much for your wonderful lesson. It is really helpful. BTW, set_multicycle_path -1 -hold -from [get_clocks fpga_clk] -to [get_clocks virt_clk] seems the right one per my timing analysis result.

0 Kudos