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Explorer
Explorer
3,327 Views
Registered: ‎06-17-2016

How to constraint ISERDES(DDR LVDS25) ?

I'm confused with the input delay constraint for ISERDES(DDR). input data and input clock are edge-aligned.

 

How to constraint the ISERDES?  clock frequency is 240MHz;

 

Thank you,

muuu

 

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1 Reply
Scholar watari
Scholar
3,270 Views
Registered: ‎06-16-2013

Re: How to constraint ISERDES(DDR LVDS25) ?

Hi muuu

 

I have two kind of answer.

Please refer the followings.

 

1) If you want to know how do you describe the constraint of rising edge and falling edge, please refer the followings.

 

set_input_delay -min <value> -clock <clock name(Use get_clocks command)> <port name(Use get_ports command)> -add_delay

set_input_delay -max <value> -clock <clock name(Use get_clocks command)> <port name(Use get_ports command)> -add_delay

set_input_delay -min <value> -clock <clock name(Use get_clocks command)> -clock_fall <port name(Use get_ports command)> -add_delay

set_input_delay -max <value> -clock_ <clock name(Use get_clocks command)> -clock_fall <port name(Use get_ports command)> -add_delay

 

2) If you want to know how do you implement it, please refer my suggestion.

 

- Use DLL or PLL and generate 1/4*T delay like method of DDR2/3/4 read access. (It is similar what you want to do)

- After that, you use 1/4*T delay as internal clock of 1st F/F. (It may add some delay to keep setup/hold timing of 1st F/F.)

- This method is easy way. But you need consider power consumption issue and DLL/PLL adjustment issue.

 

Thank you.

Best regards,

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