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Adventurer
Adventurer
8,549 Views
Registered: ‎03-30-2011

How to constraint toggle FF in ISE?

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Hi,

 

I'm working on a huge Virtex 6 design where I get a lot of unconstrained pathes in my Timing Report. To analyze some of them, I made a really simple testproject.

 

My VHDL file for testing, contains a differential clock input and a toggle output.

 

Now when checking Timing report, I have an unconstrained path from sys_clk_p_in PAD to toggle FF (which makes absolutly sense).

 

================================================================================ 
 Timing constraint: Unconstrained path analysis  
  2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints 
  0 timing errors detected. (0 setup errors, 0 hold errors) 
  Maximum delay is   3.434ns. 
 -------------------------------------------------------------------------------- 
  
 Paths for end point toggle (SLICE_X7Y118.CLK), 2 paths 
 -------------------------------------------------------------------------------- 
 Delay (setup path):     3.434ns (data path) 
   Source:               sys_clk_p_in (PAD) 
   Destination:          toggle (FF) 
   Data Path Delay:      3.434ns (Levels of Logic = 2) 
  
   Maximum Data Path at Slow Process Corner: sys_clk_p_in to toggle 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     AF10.I               Tiopi                 1.196   sys_clk_p_in 
                                                        sys_clk_p_in 
                                                        u_IBUF/IBUFDS 
     BUFGCTRL_X0Y0.I0     net (fanout=1)        0.600   clk_ibuf 
     BUFGCTRL_X0Y0.O      Tbgcko_O              0.092   u_bufg_sys_clk 
                                                        u_bufg_sys_clk 
     SLICE_X7Y118.CLK     net (fanout=1)        1.546   sys_clk 
     -------------------------------------------------  --------------------------- 
     Total                                      3.434ns (1.288ns logic, 2.146ns route) 
                                                        (37.5% logic, 62.5% route) 
  
 -------------------------------------------------------------------------------- 
 Delay (setup path):     3.434ns (data path) 
   Source:               sys_clk_n_in (PAD) 
   Destination:          toggle (FF) 
   Data Path Delay:      3.434ns (Levels of Logic = 3) 
  
   Maximum Data Path at Slow Process Corner: sys_clk_n_in to toggle 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     AE10.PADOUT          Tiopp                 0.000   sys_clk_n_in 
                                                        sys_clk_n_in 
                                                        u_IBUF/SLAVEBUF.DIFFIN 
     AF10.DIFFI_IN        net (fanout=1)        0.000   u_IBUF/SLAVEBUF.DIFFIN 
     AF10.I               Tiodi                 1.196   sys_clk_p_in 
                                                        u_IBUF/IBUFDS 
     BUFGCTRL_X0Y0.I0     net (fanout=1)        0.600   clk_ibuf 
     BUFGCTRL_X0Y0.O      Tbgcko_O              0.092   u_bufg_sys_clk 
                                                        u_bufg_sys_clk 
     SLICE_X7Y118.CLK     net (fanout=1)        1.546   sys_clk 
     -------------------------------------------------  --------------------------- 
     Total                                      3.434ns (1.288ns logic, 2.146ns route) 
                                                        (37.5% logic, 62.5% route) 
  
 -------------------------------------------------------------------------------- 
  
 Hold Paths: Unconstrained path analysis 
  
 -------------------------------------------------------------------------------- 
  
 Paths for end point toggle (SLICE_X7Y118.CLK), 2 paths 
 -------------------------------------------------------------------------------- 
 Delay (hold path):      1.492ns (data path) 
   Source:               sys_clk_p_in (PAD) 
   Destination:          toggle (FF) 
   Requirement:          0.000ns 
   Data Path Delay:      1.492ns (Levels of Logic = 2) 
  
   Minimum Data Path at Fast Process Corner: sys_clk_p_in to toggle 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     AF10.I               Tiopi                 0.580   sys_clk_p_in 
                                                        sys_clk_p_in 
                                                        u_IBUF/IBUFDS 
     BUFGCTRL_X0Y0.I0     net (fanout=1)        0.231   clk_ibuf 
     BUFGCTRL_X0Y0.O      Tbgcko_O              0.033   u_bufg_sys_clk 
                                                        u_bufg_sys_clk 
     SLICE_X7Y118.CLK     net (fanout=1)        0.648   sys_clk 
     -------------------------------------------------  --------------------------- 
     Total                                      1.492ns (0.613ns logic, 0.879ns route) 
                                                        (41.1% logic, 58.9% route) 
  
 -------------------------------------------------------------------------------- 
 Delay (hold path):      1.492ns (data path) 
   Source:               sys_clk_n_in (PAD) 
   Destination:          toggle (FF) 
   Requirement:          0.000ns 
   Data Path Delay:      1.492ns (Levels of Logic = 3) 
  
   Minimum Data Path at Fast Process Corner: sys_clk_n_in to toggle 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     AE10.PADOUT          Tiopp                 0.000   sys_clk_n_in 
                                                        sys_clk_n_in 
                                                        u_IBUF/SLAVEBUF.DIFFIN 
     AF10.DIFFI_IN        net (fanout=1)        0.000   u_IBUF/SLAVEBUF.DIFFIN 
     AF10.I               Tiodi                 0.580   sys_clk_p_in 
                                                        u_IBUF/IBUFDS 
     BUFGCTRL_X0Y0.I0     net (fanout=1)        0.231   clk_ibuf 
     BUFGCTRL_X0Y0.O      Tbgcko_O              0.033   u_bufg_sys_clk 
                                                        u_bufg_sys_clk 
     SLICE_X7Y118.CLK     net (fanout=1)        0.648   sys_clk 
     -------------------------------------------------  --------------------------- 
     Total                                      1.492ns (0.613ns logic, 0.879ns route) 
                                                        (41.1% logic, 58.9% route) 
  
 -------------------------------------------------------------------------------- 
  

So the question is, how have I to describe this scenario in my UCF, to remove this path?

 

Thanks a lot and best reagrds

Tobias

------------------------------------------------------------
Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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Highlighted
Moderator
Moderator
16,524 Views
Registered: ‎01-16-2013

Re: How to constraint toggle FF in ISE?

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@ttobsen,

 

Apply TIG (Timing ignore) constraint on this path. Check the below AR#

http://www.xilinx.com/support/answers/10025.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

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4 Replies
Highlighted
Moderator
Moderator
16,525 Views
Registered: ‎01-16-2013

Re: How to constraint toggle FF in ISE?

Jump to solution

@ttobsen,

 

Apply TIG (Timing ignore) constraint on this path. Check the below AR#

http://www.xilinx.com/support/answers/10025.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

Highlighted
Adventurer
Adventurer
8,537 Views
Registered: ‎03-30-2011

Re: How to constraint toggle FF in ISE?

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Thanks a lot for fast response!

 

I tried something like this in my UCF:

 

NET "sys_clk_p_in" TNM_NET = "TNM_sys_clk";
TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk"  6.734 ns;   # 148.5 MHz

NET "sys_clk_p_in" TNM = PADS:"Pads_sys_clk";
NET "sys_clk_n_in" TNM = PADS:"Pads_sys_clk";
TIMESPEC "TS_Pads_sys_clk" = FROM "Pads_sys_clk" TO FFS TIG;

It works perfectly.

 

Now one question for my understanding: This constraint tells the tool that it doesn't matter for me, how long the time between rising edge on the pad and the rising edge on the FF is?

 

Lets consider the following timing constraint:

 

TIMESPEC "TS_Pads_sys_clk" = FROM "Pads_sys_clk" TO FFS 4.0 ns;

Would this tell the tools, that I want to toggle the FF in at least 4 ns after sys_clk_p_in is rising? For my actual project, this is not important, but maybe I can learn something. ;)

 

Tobias

------------------------------------------------------------
Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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Professor
Professor
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Registered: ‎08-14-2007

Re: How to constraint toggle FF in ISE?

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You could do what you're suggesting, but I'm not sure if it would help.  Generally speaking the time from clock input at the FPGA pin to the clock input of a flip-flop is not constrained by itself.  What you're typically interested in is the time from the clock edge at the input pin until the flip-flop's output is stable at an output pin.  This is typically specified as an OFFSET OUT AFTER constraint, and it includes the clock delay to the flip-flop as well as the flip-flop's clock to Q and any output routing path to the pin.  The tools are quite good at doing this, and it allows you to specify the FPGA as a system component to have a particular "data sheet" clock to Q timing measured from pin to pin.

 

In the ISE GUI there is an item called "Create Timing Constraints" in the Design pane under "User Constraints."  This is a handy tool to create the timing constraints you want and it shows you graphically how they are applied.

-- Gabor
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Highlighted
Adventurer
Adventurer
8,510 Views
Registered: ‎03-30-2011

Re: How to constraint toggle FF in ISE?

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The reason I'm asking, is to decrease the number of unconstrained paths for making my timing report more readable. The output timing of the toggle_q isn't important for this example, because in the real design the toggle_q is an internal signal.

So ignoring the timing to reduce the size of my timing report is absolutly what I need.

Tobias

------------------------------------------------------------
Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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