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6,105 Views
Registered: ‎07-26-2011

How to constraints outputs to togle at once

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Hello I'm using a Spartan 3E FPGA to send 16 LVDS signals to an external system. I need to send 16 rising edges to the external system at once. In my VHDL design I used a OBUFDS. My clock is 50 MHZ and 50% duty cycle. So I set the PERIOD constraint to meet that clock specification. I set an equal OFFSET to all of my outputs. But the rising edges of the signals are not aligned. Could any one please let me know what are the other constraints that I have to set. Thanks
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Teacher eteam00
Teacher
7,565 Views
Registered: ‎07-21-2009

Re: How to constraints outputs to togle at once

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I replied in your duplicate thread in the Spartan forum.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
6,093 Views
Registered: ‎05-14-2008

Re: How to constraints outputs to togle at once

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You need to design your system and use an OFFSET OUT if the external device has certain specs to be respected.

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Teacher eteam00
Teacher
6,090 Views
Registered: ‎07-21-2009

Re: How to constraints outputs to togle at once

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What is driving the inputs to the OBUFDS output buffers?

What range of alignment is "OK", and what mis-alignment is too much mis-alignment?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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6,080 Views
Registered: ‎07-26-2011

Re: How to constraints outputs to togle at once

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Thanks for the reply.

 

What is driving the inputs to the OBUFDS output buffers?

 

I need to send a signal pattern. So I made the signal pattern insinde the VHDL code. In my current version I'm going to send a very simple signal. I past my VHDL code at the bottom of this post.

 

What range of alignment is "OK", and what mis-alignment is too much mis-alignment?

 

The best case I need allignment < 200 ps, but I'm ok with < 800 ps

 

Thank you again for answering to my post.

 

----------------------------------------------------------------------------------
-- Company:  
-- Engineer:  
--  
-- Create Date:    15:51:19 12/27/2011  
-- Design Name:  
-- Module Name:    TDCTestSource - Behavioral  
-- Project Name:  
-- Target Devices:  
-- Tool versions:  
-- Description:  
--
-- Dependencies:  
--
-- Revision:  
-- Revision 0.01 - File Created
-- Additional Comments:  
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 
library UNISIM;
use Unisim.VComponents.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity TDCTestSource is
    Port (     clk : in  STD_LOGIC;
                LED            : out STD_LOGIC;
                TestOut_p     : out STD_LOGIC_VECTOR(15 downto 0);
                TestOut_n     : out STD_LOGIC_VECTOR(15 downto 0));
end TDCTestSource;
 
architecture Behavioral of TDCTestSource is
 
signal SingleEnded : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
 
begin
 
OBUFDS_1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(0),
                                        OB    => TestOut_n(0),
                                        I => SingleEnded(0)
                                        );
 
OBUFDS_2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(1),
                                        OB    => TestOut_n(1),
                                        I => SingleEnded(1)
                                        );
 
OBUFDS_3 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(2),
                                        OB    => TestOut_n(2),
                                        I => SingleEnded(2)
                                        );
 
OBUFDS_4 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(3),
                                        OB    => TestOut_n(3),
                                        I => SingleEnded(3)
                                        );
                                        
OBUFDS_5 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(4),
                                        OB    => TestOut_n(4),
                                        I => SingleEnded(4)
                                        );
 
OBUFDS_6 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(5),
                                        OB    => TestOut_n(5),
                                        I => SingleEnded(5)
                                        );
 
OBUFDS_7 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(6),
                                        OB    => TestOut_n(6),
                                        I => SingleEnded(6)
                                        );
 
OBUFDS_8 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(7),
                                        OB    => TestOut_n(7),
                                        I => SingleEnded(7)
                                        );
 
OBUFDS_9 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(8),
                                        OB    => TestOut_n(8),
                                        I => SingleEnded(8)
                                        );
 
OBUFDS_10 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(9),
                                        OB    => TestOut_n(9),
                                        I => SingleEnded(9)
                                        );
 
OBUFDS_11 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(10),
                                        OB    => TestOut_n(10),
                                        I => SingleEnded(10)
                                        );
 
OBUFDS_12 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(11),
                                        OB    => TestOut_n(11),
                                        I => SingleEnded(11)
                                        );
 
OBUFDS_13 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(12),
                                        OB    => TestOut_n(12),
                                        I => SingleEnded(12)
                                        );
                                        
OBUFDS_14 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(13),
                                        OB    => TestOut_n(13),
                                        I => SingleEnded(13)
                                        );
 
OBUFDS_15 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(14),
                                        OB    => TestOut_n(14),
                                        I => SingleEnded(14)
                                        );
OBUFDS_16 : OBUFDS generic map ( IOSTANDARD => "LVDS_25")
                        port map(     O => TestOut_p(15),
                                        OB    => TestOut_n(15),
                                        I => SingleEnded(15)
                                        );
    
LED <= SingleEnded(0);
    
Swap : process(clk)
variable count : integer range 0 to 100 := 0;
begin
if(clk = '1' and clk'event) then
    if (count < 100) then
        count := count + 1;
    else
        count := 0;
        SingleEnded(0) <= not(SingleEnded(0));
        SingleEnded(1) <= not(SingleEnded(1));
        SingleEnded(2) <= not(SingleEnded(2));
        SingleEnded(3) <= not(SingleEnded(3));
        SingleEnded(4) <= not(SingleEnded(4));
        SingleEnded(5) <= not(SingleEnded(5));
        SingleEnded(6) <= not(SingleEnded(6));
        SingleEnded(7) <= not(SingleEnded(7));
        SingleEnded(8) <= not(SingleEnded(8));
        SingleEnded(9) <= not(SingleEnded(9));
        SingleEnded(10) <= not(SingleEnded(10));
        SingleEnded(11) <= not(SingleEnded(11));
        SingleEnded(12) <= not(SingleEnded(12));
        SingleEnded(13) <= not(SingleEnded(13));
        SingleEnded(14) <= not(SingleEnded(14));
        SingleEnded(15) <= not(SingleEnded(15));
    end if;
end if;
 
end process;
 
end Behavioral;


 

 

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Teacher eteam00
Teacher
7,566 Views
Registered: ‎07-21-2009

Re: How to constraints outputs to togle at once

Jump to solution

I replied in your duplicate thread in the Spartan forum.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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6,051 Views
Registered: ‎07-26-2011

Re: How to constraints outputs to togle at once

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Thanks eteam00

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Moderator
Moderator
6,036 Views
Registered: ‎10-04-2011

Re: How to constraints outputs to togle at once

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One big thing to do would be to make sure the logic is placed in the IOB as well. Check out the MAP commands to do this, or use the option in ISE. Since the data path from register to output pad is deterministic in these ports, with the exection of a few ps of "flight time" for flip-chip packages, the only variation would be the clock skew to each output register. Placing the registers in the same clock region / IO bank will minimize this skew variation. When the registers are in the IOB, the output timing is fixed, and then the OFFSET OUT constraint is really a report only constraint as there is nothing in the data path that can be adjusted.

 

OK, hope this helps ...

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