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How to define blackbox output clock?

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Visitor
Posts: 9
Registered: ‎05-08-2018
Accepted Solution

How to define blackbox output clock?

Hi,

There is a blackbox in my design. I added the clock definication in fdc constraint file like this:

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create_clock -name {ffb_clk} {n:u_fpga_infr.u_fpga_fb_top_gpu.u_fpga_fb.ffb_clk} -period 6 -waveform {0 3}

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The ffb_clk can be recognized by synthesis tool.

However, after place&route, vivado recognized the clock as another one:

u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/u_mig20/inst/u_ddr3_infrastructure/mmcm_clkout0

 

And there are big timing violations between these 2 clocks.

How to resolve this kind of issue?

 


Accepted Solutions
Moderator
Posts: 479
Registered: ‎11-04-2010

Re: How to define blackbox output clock?

[ Edited ]

Hi, @lisa_liu ,

What you will get from 3rd party synthesis tool and send to Vivado is edif file and XDC file.

 

You can just remove the ffb_clk related constraints from that generated XDC file.

 

 

 

 

 

 

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Scholar
Posts: 876
Registered: ‎08-07-2014

Re: How to define blackbox output clock?

@lisa_liu,

 

Can you show us your top level xdc, specially where all clocks are defined?

 

Do you have more than 1 clk in your design?

If yes, in Vivado by default all clocks are related, i.e. synchronous. For un-related clocks you have to explicitly define them as asynchronous.

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FPGA enthusiast!
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Moderator
Posts: 479
Registered: ‎11-04-2010

Re: How to define blackbox output clock?

Hi, @lisa_liu ,

You can run report_clocks to get the detailed information of these 2 clocks first.

You can also export the xdc(write_xdc XX.tcl) in the design and attach the generated tcl to us.

 

 

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Don't forget to reply, kudo, and accept as solution.
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Visitor
Posts: 9
Registered: ‎05-08-2018

Re: How to define blackbox output clock?

Hi, there are more than 200 clocks in my design. I ran "report_clocks" and got the detailed information of all the clocks. The log is too long. I only copied 3 clocks here. The "ffb_clk" is assigned to "mmcm_clkout0" in fact. But they are recognized as 2 clocks:

 

INFO: [Timing 38-35] Done setting XDC timing constraints.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2017.3 (lin64) Build 2018833 Wed Oct  4 19:58:07 MDT 2017
| Date              : Sun Sep 16 20:26:11 2018
| Host              : sc-sim-208-017 running 64-bit CentOS release 6.8 (Final)
| Command           : report_clocks
| Design            : mb_1_uB
| Device            : xcvu440-flga2892
| Speed File        : -1  PRODUCTION 1.24 03-22-2017
| Temperature Grade : C
-----------------------------------------------------------------------------------------

Clock Report


Attributes
  P: Propagated
  G: Generated
  A: Auto-derived
  R: Renamed
  V: Virtual
  I: Inverted
  S: Pin phase-shifted with Latency mode

 

Clock                                       Period(ns)  Waveform(ns)     Attributes  Sources
clk_ffb_p                                   5.000       {0.000 2.500}    P           {clk_ffb_p}
ffb_clk                                       6.000       {0.000 3.000}    P           {u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/ffb_clk_keep/I}

mmcm_clkout0                         6.000       {0.000 3.000}    P,G,A       {u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/u_mig20/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0}


====================================================
Generated Clocks
====================================================

Generated Clock     : mmcm_clkout0
Master Source       : u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/u_mig20/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1
Master Clock        : clk_ffb_p
Edges               : {1 2 3}
Edge Shifts(ns)     : {0.000 0.500 1.000}
Generated Sources   : {u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/u_mig20/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0}

 

Moderator
Posts: 479
Registered: ‎11-04-2010

Re: How to define blackbox output clock?

Hi, @lisa_liu ,

Clock mmcm_clkout0 is automatically generated by tool, which is for the output of the MMCM/CLKOUT0.

 

Which module is the black box? The MMCM? (u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/u_mig20/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst)

 

What's the relationship of module u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/ffb_clk_keep and MMCM?

Could you show the schematic of these 2 modules?

 

It seems that the clock ffb_clk is not needed to be created.

 

 

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Don't forget to reply, kudo, and accept as solution.
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Visitor
Posts: 9
Registered: ‎05-08-2018

Re: How to define blackbox output clock?

Hi, @hongh

Module u_mig20 is the blackbox. The source of u_fpga_infr/u_fpga_fb_top_gpu/u_fpga_fb/ffb_clk_keep is MMCM/CLKOUT0.

Please check the attached picture: c_ddr3_ui_clk is MMCM/CLKOUT0 actually. It's output of u_mig20 and input of ffb_clk_keep.

mig_20.png
ffb_clk_keep.png
mmcm_clkou0.png
Moderator
Posts: 479
Registered: ‎11-04-2010

Re: How to define blackbox output clock?

Hi, @lisa_liu ,

I understand you are not using Vivado synthesis tool, so the automatically generated output clock of MMCM doesn't exist during synthesis, so you intend to create one new one to replace it. 

But I think during implementation, Clock "ffb_clk" is not needed further.

 

For a primary clock (created by the command "create_clock"), the objects should be the port of FPGA, instead of the pin in fabric. The start_point difference of 2 clocks causes the unreasonable small requirement between 2 clocks.

 

 

 

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Don't forget to reply, kudo, and accept as solution.
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Visitor
Posts: 9
Registered: ‎05-08-2018

Re: How to define blackbox output clock?

Hi, @hongh

Yes, you get my point.

So shall I change the ffb_clk constraint like this:

create_generated_clock -name {ffb_clk} {n:u_fpga_infr.u_fpga_fb_top_gpu.u_fpga_fb.ffb_clk}  -source {clk_ffb_p} -multiply_by 5 -divide_by 6

 

The synthesis tool will generate xdc file that contains ffb_clk definition. And vivado will parse this xdc file. How to remove the ffb_clk during implementation?

Moderator
Posts: 479
Registered: ‎11-04-2010

Re: How to define blackbox output clock?

[ Edited ]

Hi, @lisa_liu ,

What you will get from 3rd party synthesis tool and send to Vivado is edif file and XDC file.

 

You can just remove the ffb_clk related constraints from that generated XDC file.

 

 

 

 

 

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor
Posts: 9
Registered: ‎05-08-2018

Re: How to define blackbox output clock?

Hi, @hongh

 

Ok, I will try it.