01-13-2021 11:46 PM
How can we find the critical path of our digital design architecture in Xilinx ise 14.2.
The timing constraints (worst case slack and best case achievable), which is avilable in Post and Place route report ,one of these is critical path or we have to find another timing constraint in this report. I have no idea how to determine the critical path in our design. Can you guide me how to determine.
I have attached the screenshot as well.
01-27-2021 12:18 PM
You might try opening the design in PlanAhead (basically Vivado alpha).
01-27-2021 01:03 PM
Assuming you are using an FPGA not a CPLD
then you need to generate some constraints, and run the tools
At the least , constrain the clock in
whats the device,
can you share your timing constraints
Why you not using 14.7 ?
Once you have timing constraints, the report generated when you synthesis shows the timing of the worst paths
BTW: Ensure you simulate before you synthesise,
no point synthesising something that has not been shown to work in simulation.