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malikasher267
Visitor
Visitor
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Registered: ‎02-26-2019

How to determine the critical path

How can we find the critical path of our digital design  architecture in Xilinx ise 14.2.

The timing constraints (worst case slack and best case achievable), which  is avilable in Post and Place route report ,one of these is critical path or we have to find another timing constraint in this report. I have no idea how to determine the critical path in our design. Can you guide me how to determine.

I have attached the screenshot as well.

CP.jpeg
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maps-mpls
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Mentor
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Registered: ‎06-20-2017

You might try opening the design in PlanAhead (basically Vivado alpha). 

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***
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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Assuming you are using an FPGA not a CPLD

 

then you need to generate some constraints, and run the tools

      At the least , constrain the clock in 

 

Few questions

whats the device,

  can you share your timing constraints 

   Why you not using 14.7 ? 

 

Once you have timing constraints, the report generated when you synthesis shows the timing of the worst paths

 

BTW: Ensure you simulate before you synthesise,

  no point synthesising something that has not been shown to work in simulation.

 

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