cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
3,929 Views
Registered: ‎06-25-2015

How to determine when to contrain a clock signal?

Jump to solution

Hello, 

 

I looking for some clarification on constraining clock signals. I have a differential clock coming in through the FMC on clock capable pins. I have constrained this clock using

 

CLKOUTAP/CLKOUTAN --> IBUFDS --> BUFG --> clka

 

create_clock -name clka - period 12.412 [ get_ports CLKOUTAP]

 

I then use clka to as input to a mmcm (using clock wizard) to multiply by 2.

 

Should I need to constrain the output of the mmcm using create_generated_clock?

 

I read in ug903 that auto generated clocks do not need to be manually constrained. Wouldn't this mmcm be an auto-generated clock. 

 

I am using kc705 eval brd, vivado 2016.1

 

Thank you for your time

 

Adam Gropp

 

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Guide
Guide
7,225 Views
Registered: ‎01-23-2009

Vivado automatically creates generated clocks on the outputs of known "clock modifying blocks". For the moment, these are

  - MMCM

  - PLL

  - BUFR (which can do integer division)

 

All other clocks need to be manually constrained

  - Input ports (create_clock)

  - gated clocks (create_generated_clock)

     - ideally using BUFGCE/BUFHCE, but technically even fabric generated clocks can be constrained

       - fabric generated clocks are not recommended

  - forwarded output clocks generated by an output flip-flip, ODDR or OSERDES (create_generated_clock)

 

Clocks propagate normally through buffers (BUFG, BUFH, BUFR in pass-through mode, BUFIO) and even combinatorial logic (not recommended).

 

Avrum

View solution in original post

2 Replies
Highlighted
Guide
Guide
7,226 Views
Registered: ‎01-23-2009

Vivado automatically creates generated clocks on the outputs of known "clock modifying blocks". For the moment, these are

  - MMCM

  - PLL

  - BUFR (which can do integer division)

 

All other clocks need to be manually constrained

  - Input ports (create_clock)

  - gated clocks (create_generated_clock)

     - ideally using BUFGCE/BUFHCE, but technically even fabric generated clocks can be constrained

       - fabric generated clocks are not recommended

  - forwarded output clocks generated by an output flip-flip, ODDR or OSERDES (create_generated_clock)

 

Clocks propagate normally through buffers (BUFG, BUFH, BUFR in pass-through mode, BUFIO) and even combinatorial logic (not recommended).

 

Avrum

View solution in original post

Highlighted
Adventurer
Adventurer
3,895 Views
Registered: ‎06-25-2015

@avrumw Awesome thank you very much. I believe I was able to see vivado create the constraint. I had constrained the clock output and vivado gave a critical warning stating that a constraint override took place. The previous constraint was self generated and the new constraint was the one I made. Thank you for your time.

 

Adam

0 Kudos