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zan_zhan@amat.com
Adventurer
Adventurer
986 Views
Registered: ‎01-24-2018

How to pack reg into IOB in HD bank of Kintex Ultra Plus without pulse width violation

 

Does any know How to pack reg into IOB in HD bank of Kintex Ultra Plus without pulse width timing violation?

 

I am using 200M clock to drive signals output as SDR which are assigned to HD bank.

With "set_property IOB ture [get ports xxxx]" in xdc, I get below warning after Synthesis and also it looks like these signals are still not packed into IOB. 

 

111.png

 

Thanks in advance!

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2 Replies
pthakare
Moderator
Moderator
976 Views
Registered: ‎08-08-2017

Hi zan_zhan@amat.com

 

Please refer to the below AR and let us know if you missing anything in writing the IOB attribute/constraints.

https://www.xilinx.com/support/answers/66668.html

 

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

I haven't done much work with UtraScale, but I believe that these flip-flops are packed into the IOB...

 

The Location is "HDIOLOGIC_...", which looks like the IOB flip-flops. If they weren't in the IOB flip-flops, the Location would be something like SLICE_XxxYyy...

 

These messages are telling you that you are clocking these flip-flops too fast. While you claim that you are using a 200MHz clock, the tools seem to think that they are being clocked at 240Mhz. Furthermore, (and, again, I am not an UltraScale expert) it is telling you that these IO (the HDIO) cannot be clocked at more than 125MHz... If you look at DS922, Table 23 shows that the maximum bit rate for the HD banks are, in fact, 125Mbps in some configurations...

 

Avrum