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Voyager
Voyager
12,758 Views
Registered: ‎07-28-2008

How to reduce Data Path Delay

1.964ns logic, 5.521ns route

 

Requirement 4ns, Data Path Delay 7.485ns (Levels of Logic = 1)

 

I have more than 100 these violations.

 

Virtex4, how to resovle them?

 

thanks

 

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Historian
Historian
12,757 Views
Registered: ‎02-25-2008


legendbb wrote:

1.964ns logic, 5.521ns route

 

Requirement 4ns, Data Path Delay 7.485ns (Levels of Logic = 1)

 

I have more than 100 these violations.

 

Virtex4, how to resovle them?

 

thanks

 


Tighten up your logic?

 

Loosen your timing constraint?

 

-a

----------------------------Yes, I do this for a living.
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Voyager
Voyager
12,723 Views
Registered: ‎07-28-2008

I have only one level logic, I think is is no way to tighten no more.

But the major portion of the delay is route delay, which can be seen  Flooplan-Implemented view. But don't know how to use it other than for pin assignments. Any recommendation, or reference?

 

I'm targeting xc4vsx35-10 at 250MHz.

 

Found http://www.xilinx.com/support/training/rel/arch-wiz-floorplan-editor.htm

any other reference? 

 

Thanks again.

Message Edited by legendbb on 02-25-2009 10:04 AM
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Xilinx Employee
Xilinx Employee
12,711 Views
Registered: ‎11-28-2007

I would recommend you use PlanAhead for floorplanning. A lite version of PlanAhead is included in 10.1.03. The tutorials installed with the tool should get you started in the right direction.

 

Cheers,

Jim

 

Cheers,
Jim
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Explorer
Explorer
12,558 Views
Registered: ‎09-18-2007

What would you do in Floorplanner to improve this? Manually move gates around? Surely the PAR tool should do the gate moving when it seens the constraint timing?

 

Thanks

David

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Observer
Observer
8,896 Views
Registered: ‎08-14-2007

So have you resolve them?

 

I ran into similar problems.

 

Thank you very much!

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Xilinx Employee
Xilinx Employee
8,802 Views
Registered: ‎05-14-2008

Here is a document for Floorplanning for Performance using PlanAhead:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/PlanAhead_Tutorial_Design_Analysis_and_Floorplanning_for_Performance.pdf

 

Also the chapter on Timing Closure from UG612 would be helpful- Chapter 7, page 151 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/ug612.pdf was written to help users resolve timing issues in their designs. See the scenarios of page 171.