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Adventurer
Adventurer
3,748 Views
Registered: ‎11-11-2015

How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi everyone,

 

I'm working on a Vivado project related with ADC and I met some timing problem. Can anyone give me some suggestions?

I created a project to demap the sampled data from ADC12J4000. The block design is shown as follows.

pic1.png

The ADC demapping block demaps the ADC sampled data into 8 parallel channels, and each channel has a 500MHz clock.

pic2.png

The implemented timing report shows that all the timing violations are setup negative slacks. 

pic3.png

pic4.png

pic5.png

pic6.png

I already used pipelining to reduce the combinational logic delay, and the logic delays in the failed paths are small compared to the clock period. I noticed that net delays are relatively large compared to the logic delay. Since period of each clock cycle is 2ns, the timing is very difficult to be met.

 

I also tried different implementation strategies, but the timing violations still exist. However, if I decrease the clock frequency of each channel to 200MHz, the timing can easily be met.

 

I'm wondering if there are some methods to reduce the net delays, but I cannot find a solution from Xilinx forum and documents.

Here I attached timing report of this project. Could you tell me the general methods to reduce the net delays?

 

Thank you very much.

 

Regards,
Tong

 

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Historian
Historian
5,637 Views
Registered: ‎01-23-2009

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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500MHz is always going to be challenging - it is approaching the upper limit of what you can do in the FPGA.

In addition, getting signals to and from RAMs is always challenging in (even at lower speeds). The combination is pretty bad.

In your case, you are trying to go from a RAM, through two LUTs, and to an SRL at 500MHz. I am not surprised that this doesn't meet timing.

The RAM column is a separate column - it is, by definition, some distance away from other fabric logic. At 500MHz, you cannot go very "far" in routing in one clock cycle. Add that to the two LUT delays, and its just too much.

I can see (from the delay) that the RAM is already using the output register - at 500MHz, this is pretty much required. I can't tell if this output register was selected through instantiation of the RAM primitive, or was merged in to the RAM through inference. In either case, to have any chance here, you need another pipeline stage on the outputs of the RAM - one to be placed in the DOA/DOB register and one more just after that to allow for the routing delay back from the RAM column to the fabric logic.

At 500MHz, you therefore need 3 clock cycles of latency for the RAM reads (the RAM read itself, the DOA/DOB register and one more fabric register). After that you can do some processing with the result.

Avrum

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12 Replies
Historian
Historian
5,638 Views
Registered: ‎01-23-2009

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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500MHz is always going to be challenging - it is approaching the upper limit of what you can do in the FPGA.

In addition, getting signals to and from RAMs is always challenging in (even at lower speeds). The combination is pretty bad.

In your case, you are trying to go from a RAM, through two LUTs, and to an SRL at 500MHz. I am not surprised that this doesn't meet timing.

The RAM column is a separate column - it is, by definition, some distance away from other fabric logic. At 500MHz, you cannot go very "far" in routing in one clock cycle. Add that to the two LUT delays, and its just too much.

I can see (from the delay) that the RAM is already using the output register - at 500MHz, this is pretty much required. I can't tell if this output register was selected through instantiation of the RAM primitive, or was merged in to the RAM through inference. In either case, to have any chance here, you need another pipeline stage on the outputs of the RAM - one to be placed in the DOA/DOB register and one more just after that to allow for the routing delay back from the RAM column to the fabric logic.

At 500MHz, you therefore need 3 clock cycles of latency for the RAM reads (the RAM read itself, the DOA/DOB register and one more fabric register). After that you can do some processing with the result.

Avrum

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Adventurer
Adventurer
3,681 Views
Registered: ‎11-11-2015

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi @avrumw,

 

Thank you very much.

 

I'll try to add more pipeline stages and give you feedback if I get any new results.'

 

Regards,

Tong

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Adventurer
Adventurer
3,602 Views
Registered: ‎11-11-2015

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi @avrumw,

 

I tried to add more pipeline stages and the timing has improved. However, I cannot get rid of the setup timing violation.

 

I decreased the sampling rate of ADC to 2.7GHz so that each channel has a frequency of 337.5MHz. With a lower clock frequency, the timing could be met. This sampling frequency will be sufficient for my project.

 

Thanks.

 

Tong

 

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Adventurer
Adventurer
1,579 Views
Registered: ‎08-30-2018

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Dear @onlinext and @avrumw,

 

I just now tumbled into this post while searching for an answer to my problem. I have a block design that I used AXI Interconnect in order to enable the Microblaze to talk to the UART, GPIO, SPI, and DDR3.

 

I have started with an AXI Interconnect with 1 Slave (connected to the Microblaze) and 1 Master (connected to UART at the first stage) and could talk to the UART.

 

For the next modules, I added the number of Master portsin AXI Intercommect finally by 4 to be able to talk to all four modules mentioned above.

 

I see from timingreport when I increase the number of Master ports in AXI Interconnect, the WNS (Worst Negative Slack) becomes smaller and smaller that will become negative if I increase the number of Master ports in AXI Interconnect.

 

I know that it is obvious becsuseI am increasing the fanout and hense decreasing the slack time due to the routing + logic delays added to the design.

 

I see in this post that @onlinext has mentioned he added "Pipeline stages" to his design and could improve the timing slacks !! I have search and probably it is "AXI  Register Slice" that can be used as a pipeline stage. Am I right?? Di you @onlinext used also this module to improve your slack time? I did a practice with this module but it decreased the slack time more that before!

 

I am really stuck and I think you guys may give me a solution and guide to overcome my negative slack barrier cscause of mentiond story.

 

Kind helps and guides are in advance appreciated.

 

Bests,

Daryon

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Adventurer
Adventurer
1,555 Views
Registered: ‎11-11-2015

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi @daryon,

 

I didn't use AXI interconnect in this design, so I don't know if "AXI Register Slice" will be helful or not.

 

My design was unable to meet the timing constraint when the clock frequency is 500MHz. In order to meet the timing constraint, I decreased the clock frequency to 337.5MHz.

 

Regards,

Tong

 

 

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Adventurer
Adventurer
1,485 Views
Registered: ‎08-30-2018

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi @onlinext,

 

I used AXI interconnect and enabled the REgister slices for this IP. It works very well and my problem got solved! :)

 

Regards,

Daryon

Explorer
Explorer
886 Views
Registered: ‎08-31-2016

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi @daryon,

I'm facing a similar problem. I have couple of questions for you

1) For Enable register slice, there's a drop down menu with options like outer,auto & outer-auto. Which one did you select?

2) Did you enable register slice for both slave interface and master interface?

Warm wishes,

Vinay 

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Dear @vinay_shenoy,

Prior to answer your questions, please have a look onTable 3-6 on page 99 of PG059 to see the differences between "outer" and "auto" type register slices.

1. Choose Outer for the register slice

2. Since your clock frequency is very high (~500MHz), enabling the slice register only at the SLave side should suffice and solve the problem. It depends on the amount of negative slack (WNS) that you currently have in your design. For example, if it is around 1-2 ns, the slice register only at the Slave side should be good, but if the WNS is around 10's of nsec, then please enable the register slices for both Slave and Master sides.

Hope it can help.

Bests,

Daryon

Explorer
Explorer
867 Views
Registered: ‎08-31-2016

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Thank you @daryon
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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Dear @vinay_shenoy,

 

Did your problem get solved? Please let me know if you have more assistance. I will be more than happy to give a help. Other peoples here help me out with my threads and I will do my best to do the same for the others.

Bests,

Daryon

Explorer
Explorer
747 Views
Registered: ‎08-31-2016

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi @daryon
Happy New Year 2019!
Register slices across SI & MI and inclusion of a fifo (32) for AXI Interconnect has helped me reduce the slack to a greater extend. However I still face a -12 ns TNS.
Not sure how to further reduce them

Best regards & wishes,
Vinay Shenoy

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Adventurer
Adventurer
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Registered: ‎08-30-2018

Re: How to reduce the net delay of a design with 500MHz clock in Vivado

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Hi @vinay_shenoy,

Happy new year to you too. All the bests in 2019.

However, I still face a -12 ns TNS.

This means that the clock frequency that you have chosen for your design is higher than data transfer rate between the IPs used in the design. Please try to reduce the clock frequency that feeds the s_axi_aclk, Sxx_CLK, and ACLK of the IPs in the design. Please do not forget to use a reset signal synchronous with that reduced clock signal for the s_axi_aresetn, and aresetn of IPs.

 

Hope it can help.

Bests,

Daryon