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Registered: ‎02-22-2010

How to report specific timing paths with TCL?

Hi,

 

I want to report timing from/to some instantiated DDR FFs using TCL, but haven't succeeded.

 

    ...

    WARNING:TimingToolsC - "*/s_dqs_high" is not a valid Flip-flop name.      # and like ...
    ...

 

See the different non-working "timing_analysis set_endpoint" TCL commands below.

 

I've managed to report timing to/from a FF declared as a signal in a clocked process, when I include the full

hierarchical path.

  

 

I've looked through the "Constraints Guide", "Development System Reference Guide:TCL", "Xilinx Timing Constraints User Guide"

and the Forum, but haven't found anything useful.

 

 

Regards,

 

xlxuserafsystem 

 

 

--------- TCL timing script --------------------------------------

 

# open project.
project open ./rumf.ise

 

# name of timing report.
set name "ddr_io_ana"

 

# new timing analysis case.
timing_analysis new analysis -name ${name}

timing_analysis set ${name} report_format ascii
timing_analysis set ${name} report_name ${name}
timing_analysis set ${name} paths_per_constraint 1
timing_analysis set ${name} report_datasheet false
timing_analysis set ${name} report_timegroups false

timing_analysis set ${name} analysis_type endpoints


#--- works ---

 

# "set_endpoints" doesn't work with to/from at the same time.

 

timing_analysis set_endpoints ${name} to ffs \
                rumf_1/ext_mem_tx/ddr2_if_1/u_ddr_data_path/s_dqs_high

 

#timing_analysis set_endpoints ${name} from ffs \
#                rumf_1/ext_mem_tx/ddr2_if_1/u_ddr_data_path/s_dqs_high


#--- doesn't work ---

#timing_analysis set_endpoints ${name} to ffs \
#                rumf_1/ext_mem_rx/ddr2_if_1/u_ddr_data_path/g_ddr_dq[2].u_ddrin/FDRSE0

 

#timing_analysis set_endpoints ${name} to ffs \
#    rumf_1/ext_mem_rx/ddr2_if_1/u_ddr_data_path/g_ddr_dq\[63\].u_ddrin/*

 

#timing_analysis set_endpoints ${name} to ffs \
#    rumf_1/ext_mem_rx/ddr2_if_1/u_ddr_data_path/*/*

 

#timing_analysis set_endpoints ${name} to ffs \
#                rumf_1/ext_mem_rx/ddr2_if_1/u_ddr_data_path/g_ddr_dq<2>.u_ddrin/FDRSE0

 

#timing_analysis set_endpoints ${name} to ffs \
#                "rumf_1/ext_mem_rx/ddr2_if_1/u_ddr_data_path/*"

 

#timing_analysis set_endpoints ${name} to ffs \
#                "*/s_dqs_high"

 

 

timing_analysis run ${name} -overwrite

 

---- RTL ------------------------------------------------------

 

ARCHITECTURE rtl OF ddr_data_path IS

......

  
  COMPONENT ofddrtrse IS
    PORT (
      O  : OUT STD_LOGIC;
      C0 : IN  STD_LOGIC;
      C1 : IN  STD_LOGIC;
      CE : IN  STD_LOGIC;
      D0 : IN  STD_LOGIC;
      D1 : IN  STD_LOGIC;
      R  : IN  STD_LOGIC;
      S  : IN  STD_LOGIC;
      T  : IN  STD_LOGIC
      );
  END COMPONENT ofddrtrse;
 
  COMPONENT ifddrrse IS
    PORT (
      Q0 : OUT STD_LOGIC;
      Q1 : OUT STD_LOGIC;
      C0 : IN  STD_LOGIC;
      C1 : IN  STD_LOGIC;
      CE : IN  STD_LOGIC;
      D  : IN  STD_LOGIC;
      R  : IN  STD_LOGIC;
      S  : IN  STD_LOGIC
      );
  END COMPONENT ifddrrse;

  SIGNAL s_logic_zero           : STD_LOGIC;
  SIGNAL s_logic_one            : STD_LOGIC;
  SIGNAL s_dqs_high             : STD_LOGIC;
  SIGNAL s_wrdata_p             : STD_LOGIC_VECTOR(63 DOWNTO 0);
  SIGNAL s_wrdata_n             : STD_LOGIC_VECTOR(63 DOWNTO 0);
 
BEGIN

 

............

 

  p_wr_dqs_clk: process(i_clk_ddr_90_inv) IS
  BEGIN
    IF (rising_edge(i_clk_ddr_90_inv)) THEN
      s_dqs_high <= i_dqs_high;
    END IF;
  END PROCESS p_wr_dqs_clk;
 
  g_ddr_dq: FOR i IN 0 TO 63 GENERATE
    u_ddrout: OFDDRTRSE
      PORT MAP (
        O   => b_ddr_dq(i),
        C0  => i_clk_ddr_0,   
        C1  => i_clk_ddr_0_inv,
        CE  => s_logic_one,
        D0  => s_wrdata_n(i),
        D1  => s_wrdata_p(i),
        R   => s_logic_zero,
        S   => s_logic_zero,
        T   => i_write_active
        );
    u_ddrin: IFDDRRSE
      PORT MAP (
        Q0  => o_rddata_p(i),
        Q1  => o_rddata_n(i),
        C0  => i_clk_ddr_rd,   
        C1  => i_clk_ddr_rd_inv,
        CE  => s_logic_one,
        D   => b_ddr_dq(i),
        R   => s_logic_zero,
        S   => s_logic_zero
        );
  END GENERATE g_ddr_dq;

END ARCHITECTURE rtl;

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