06-20-2019 05:58 AM
Hello everyone, i use Vivado 18.2 and i have a problem with my design. I want to connect 2 nets in a SR lach and this nets have to be similar in delay net (ps). Is there any tool that can fix line delays to be similar?
thank you for help me and regards.
06-20-2019 09:21 AM
Vivado is designed for synchronous design, and as such, the concept of "matching delays" is not something that Vivado cares about, so there is no constraint that will do this for you.
You may be able to rougly bound a path with a combination of set_min_delay and set_max_delay, but that has to be done with a full path (not a net) and will have to take into account that the analysis of the min and max will be done at different process corners - this may help, but it is not what it is meant to do, so isn't a "simple solution".
If you really want to control this, you may need to think about manually routing the nets and then locking them to specific routing resources. This too is pretty complicated to do.
In summary, FPGAs (and their tools) are not meant to do things like this. If you want to try and get an FPGA (and its tools) to do things like this (i.e. for research purposes) then you will have to design your own mechanism for doing them in spite of the tools...
06-20-2019 07:35 PM
Like Avrum said, there is not a direct constraint to achieve what you expect.
One possible way is to try multiple implementations and check the delays of the two nets in each run. If you're lucky to get a run with similar delays of the two nets, you can then fix the routing of the two nets.