12-23-2008 04:39 PM
I'm using both edges of a clock from a DCM ( I'm not using the CLK180 due to lack of BUFGs) the datasheet refers to DCM and Clock tree Duty cycle distortion. These figures don't appear to be taken into account in the timing analyzer ( 10.1SP3). Is the best way just to increase the clock rate to effectively take it into account or have I missed something?
12-29-2008 09:23 AM
the tools automatically take rising and falling edge clocks into account.
there are no dual-clock FFs in the FPGA fabric except in the Input-Output-Block, so I assume you refer to these FFs.
timing analyzer should be correct and you don't use one of the 2 edges of the clock.
if you don't see it in timing analyzer, try to increase the reported amount of paths.
maybe you will find the following whitepapers of interest:
http://www.xilinx.com/support/documentation/white_papers/wp257.pdf (about period constraints)
http://www.xilinx.com/support/documentation/white_papers/wp237.pdf (about offset constraints and DDR-FF offset constraints)
12-30-2008 05:22 AM
My question was about clock distortion. The clock out of the DCMs isn't 50:50 ( it will be close but not exact) and after is has gone though buffers and clock tree it will be worse. The datasheet says the distortion in my case may be upto 410ps. This figure appears to be missing from the Timing Analyzer report.