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Visitor sheng.liu
Visitor
362 Views
Registered: ‎09-25-2018

How to solve this timing issue in ISE14.7?

Hi,

When I build my ISE project, target FPGA unit is xc6slx9-2csg324 and the environment is ISE14.7, the timing constraints report shows the timing isn't closed. The captured graphical UI is attached. Can you help me to analysis and solve this timing issue?

Thanks in advance.

Untitled.png

 Best regards,

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19 Replies
Participant evant_nq
Participant
342 Views
Registered: ‎07-18-2018

Re: How to solve this timing issue in ISE14.7?

Hi sheng.liu

 

Can you share what the timing Path failure looks like for both the setup and hold corner?

(The values it shows that don't add up to a positive slack)

 

and then the constraint that you defined that represents this path?

That would be the minimum needed to understand where it's losing margin that might be able to be made up elsewhere or be adjusted.

 

 

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Visitor sheng.liu
Visitor
325 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

Thank you for your reply. I captured the setup and hold corner like this. Is it valuable? I don't know how to analyze and modify the right corner to close the timing. And I don't do anything constraint in my .ucf file except some pin definition and group constraint. Can you give me some suggestions? Thank you very much.

Untitled.png

 Best regards,

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Mentor hgleamon1
Mentor
314 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

 

I see two things from your timing report:

1. You have different launch and capture clocks. Are these clocks synchronous or have you otherwise ensured that you are crossing clock domains correctly?

2. You have six levels of logic in the timing path. Is it possible to reduce this or pipeline the datapath?

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"That which we must learn to do, we learn by doing." - Aristotle
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Visitor sheng.liu
Visitor
308 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

Thank you for your reply.

1. The source of FPGA clock is the external crystal oscillator of 50M. the 50M is put into BUFG and DCM IPcore and generate the 100M used for ARM GPMC interface, the 200M used for pulse generation. So can I understand these clocks are sync and have same phase? For such clocks, what operations do I need to do in the .ucf file to improve the timing?

2. How can I see six levels of logic in the timing path? And how should I do analysis these six level timing and modify in the .ucf file?

Thank you very much.

Best regards,

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Newbie jillian357
Newbie
295 Views
Registered: ‎10-23-2018

Re: How to solve this timing issue in ISE14.7?

Xilinx does not officially support using Windows 8.1 or Windows 10 with ISE Design Suite. Thus the factory have not tested ISE in Win10 for stability issues, though it might get installed and sometimes work without problems. Try using supported OS as per AR18419, and check if you are facing similar issue since you have already tried searching forums/solutions, redownloaded ISE 14.7 and even reformatted your computer. 

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Mentor hgleamon1
Mentor
293 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

1. If your clocks come from the same source and DCM it is likely that they are synchronous (especially as they are 100M and 200M). So that should be OK. I assume you have correctly specified a TIMESPEC in your .ucf for the incoming 50M external clock? If so, then the tools are already doing their job. You can look in the Translation report in the ISE GUI to see how the tools have interpreted your incoming and generated clocks (you should see that the 100M and 200M clocks are derived from the same DCM).

2. In your previous screenshot you can see the datapath delay is 4.588 ns for this datapath. It also states there are 6 levels of logic. This means you have some combinatorial logic between flip flops. It looks like the path has some inversion of a clear signal and also refers to some counter state. It may be possible to pipeline this logic or remove unnecessary combinatorial steps. Without seeing your code for the gpmc_ncs_d2 FF and how it relates to the pulse_num_count_10 FF, it's not possible to for me to guess how to fix the timing but I would start by looking at those signals in your code.

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"That which we must learn to do, we learn by doing." - Aristotle
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Mentor hgleamon1
Mentor
283 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?


@jillian357 wrote:

Xilinx does not officially support using Windows 8.1 or Windows 10 with ISE Design Suite. Thus the factory have not tested ISE in Win10 for stability issues, though it might get installed and sometimes work without problems. Try using supported OS as per AR18419, and check if you are facing similar issue since you have already tried searching forums/solutions, redownloaded ISE 14.7 and even reformatted your computer. 


How is this even remotely relevant to the topic or problem described?

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"That which we must learn to do, we learn by doing." - Aristotle
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Visitor sheng.liu
Visitor
279 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

Thank you for your reply.

1. Yes I indeed make the 50M initial source clock constraint in .ucf file:

NET "clk_in" LOC = "C11";
NET "clk_in" TNM_NET = clk_in;
TIMESPEC TS_clk_in = PERIOD "clk_in" 50 MHz HIGH 50%;

So is it will be right?

2. For generating the pulse signal, I design some combinatorial logic and counter in my code, but I don't how to modify them to close timing...... Do I have to adjust the datapath from gpmc_ncs_d2 to pulse_num_cnt to close the timing? Or can I just adjust the .ucf file to meet the system's timing requirements but not the FPGA code? You mean start by looking at those signals in my code, can I send my code to you to help to analysis the timing?

Thank you very much.

Best regards,

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Mentor hgleamon1
Mentor
274 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

1. Your timespec looks OK. The tools should be able to handle that. I assume that pin C11 is a clock capable pin?

2. If you attach or embed your code here specific to those signals/counters, we can try to identify a way to improve the timing for the datapath. I don't think you'll be able to fix this with a .ucf constraint.

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"That which we must learn to do, we learn by doing." - Aristotle
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Visitor sheng.liu
Visitor
277 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

Thank you for your reply. I checked the schematic again and found C11 is the GCLK pin. Maybe it would be better for me to send the FPGA code to your personal email? Thank you in advance.

Best regards,

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Mentor hgleamon1
Mentor
270 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

I sent you a PM.

However, if we deal with this offline there will be no obvious closure for those people who are following this topic or subsequently search for similar solutions to similar problems in the Community.

It would be better, for the Community, to bring your code here rather than privately but it is your choice.

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"That which we must learn to do, we learn by doing." - Aristotle
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Visitor sheng.liu
Visitor
265 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

I think your advice is right. My code is attached. These are two submodule, one is gpmc and the other is pulse generator. They are be connected in the top level. The interface name defined in the top code are the same. Can you analyze them and give me some help?

Thank you very much.

Best regards,

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Mentor hgleamon1
Mentor
257 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

Right, I'm no expert in Verilog but I've tried to do my best.

The signal gpmc_ncs_d2 is used in a number of asynchronous multiplexers for the pulse_sel signal. It looks like the pulse_sel<0> signal is then used to combinatorially generate the pulse_clr_temp signal, which is then used to synchronously reset the pulse_num_cnt signal.

As you are crossing from a 100M clock domain to a 200M clock domain (even though the domains are synchronous) you have effectively halved the clock period available to combinatorially produce the signals.

I don't know what your timing/latency requirements are but I would first look to see if you can synchronise your combinatorial processing to reduce the levels of logic that the gpmc_ncs_d2 signal has to pass through.

 

i.e. can you put the following lines into a clocked process?

assign pulse_sel[1]  = ((gpmc_ncs_d2 == 1'b0) && ((gpmc_a_reg == 5'h04) || (gpmc_a_reg == 5'h05) || (gpmc_a_reg == 5'h06))) ? (~gpmc_nwe_d3) : 1'b0;
assign pulse_sel[0]  = ((gpmc_ncs_d2 == 1'b0) && ((gpmc_a_reg == 5'h07) || (gpmc_a_reg == 5'h08) || (gpmc_a_reg == 5'h09))) ? (~gpmc_nwe_d3) : 1'b0;

assign pulse_clr_temp = pulse_clr | pulse_sel;
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"That which we must learn to do, we learn by doing." - Aristotle
Visitor sheng.liu
Visitor
229 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

Thank you for your good suggestion. I modified the signal of pulse_sel and pulse_clr_temp into sequential logic. The pulse_sel is in the GPMC module and clk = 100M, and pulse_clr_temp is in the pulse_gen module and clk = 200M. The timing report captured is:

Untitled.png

So it seems the setup path slack error become better (from -0.7 to -0.5), though it's still wrong,and the hold path slack error become right, compared with previous reports. Is there anything else that can be modified?

I don't know what your mean about timing/latency requirements. My clock is 50M into FPGA, and 100M for GPMC interface, 200M for pulse generator. Is it enough for my design or constraint?

Best regards,

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Mentor hgleamon1
Mentor
218 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

Look carefully at the names of the signals in the failing timing paths. The failing end point is no longer the same. In effect you have corrected your first timing failures and now have identified some new ones due to the change in your logic.

 

You have three different failing end points, namely:

1. pulse_period_13 (i.e. the 13th bit in the pulse_period signal vector)

2. pulse_period_15 (i.e. the 15th bit in the pulse_period signal vector)

3. pulse_trig_reg_1 (i.e. the first bit in the pulse_trig_reg signal vector)

 

I think you should apply similar synchronising techniques as I suggested previously to the generation of the pulse_address signal, i.e.

assign pulse_address = ((pulse_sel == 2'b01) || (pulse_sel == 2'b10)) ? gpmc_a_reg : 5'h00;

 

When I mentioned timing and latency, I was referring to, within your system, what the timing or latency requirements are to process the data from input to output. For example, what are your requirements, either in seconds (or some fraction thereof) or in numbers of 50M clock cycles, for you to receive your data and produce an output?

You will improve internal timing by pipelining signals but if pipelining causes an unacceptable change in your system performance because the additional registers cause system latency, then you will need to find an alternative solution.

It may be that your system does not care too much about latency, e.g. it doesn't really matter how many clock cycles it takes to process the data as long as some data come out eventually, in which case, pipelining will definitely help your cause.

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"That which we must learn to do, we learn by doing." - Aristotle
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Visitor sheng.liu
Visitor
208 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

Thank you very much.

1. I modified the pulse_address signal to clock timing design, and the report become better (reduce slack from -0.5 to -0.2):

Untitled.png

2. I got rid of such register: pulse_address_reg, and changed code like this: output reg  [ 4:0] pulse_address. So the assign statement is also be deleted. This seems be benefit with the timing.

assign pulse_address = pulse_address_reg; // delete this line and define output reg signal

3. My project has no particular latency requirement. I just want to run the pulse in 200M.

Best regards,

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Mentor hgleamon1
Mentor
199 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

You should, by now, have the idea of how to interpret the failing paths, how those paths relate to flip flops in your design and how to investigate and recode your design to increase the pipelining of signals to give you better timing margins.

Now you should examine the gpmc_a_reg and pulse_address signals.

Of  some interest is the failing path you have highlighted in your most recent post. For the pulse_num_cnt signal you can see that there is a level of logic that is a reset signal with a high fanout and quite a long delay - looking at your code this looks like it is the pulse_clr_temp signal.

Do you really need this as a reset? You have a global reset that is already resetting the pulse_clr signal and resets most of your other synchronous signals. Perhaps you can rationalise your reset strategy.

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"That which we must learn to do, we learn by doing." - Aristotle
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Visitor sheng.liu
Visitor
67 Views
Registered: ‎09-25-2018

Re: How to solve this timing issue in ISE14.7?

Hi,

Thank you again for your help. I'll reconsider the logic of my pulse generation. It seems only modify the FPGA code to close the timing. Anyway, thank you very much for your suggestion.

Best regards,

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Mentor hgleamon1
Mentor
51 Views
Registered: ‎11-14-2011

Re: How to solve this timing issue in ISE14.7?

 

Generally speaking, it is the HDL that will define your make-or-break with regards to timing. There are some tricks that can be done with flip flop placement and maximum delays of certain paths but I think your timing issues can be solved by examining your design a little closer.

Please come back to this thread if you need some more assistance. Good luck!

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"That which we must learn to do, we learn by doing." - Aristotle
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