cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
18,047 Views
Registered: ‎07-16-2014

How to treat asynchronous inputs to be excluded from STA

Jump to solution

I have an asynchronous input SELF_DONE. That input goes into a 2-stage synchronizer (2 flip-flops) that runs on a clock that is completely asynchronous to that SELF_DONE input.

 

In Vivado, after I run check_timing commnad I get the following messages:

1)

unconstrained pins for maximum delay:

<some_path>/self_done_demet_reg[0]/D

2)

ports with no input delay:

SELF_DONE

 

I do not care about input or maximum delay in this case since I know that the SELF_DONE input is completely asynchronous and its change may come at any time. How can I simply remove the path from the SELF_DONE input to the demet register pin (self_done_demet_reg[0]/D) from analysis so that I do not get those two messages after running the check_timing command?

 

I tried to set the following false path but after running the check_timing command it had no impact:

set_false_path -from [get_ports SELF_DONE] -to [get_pins <some_path>/self_done_demet_reg[0]/D]

 

Could you please give me some advice? Thank you very much!

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Guide
Guide
28,448 Views
Registered: ‎01-23-2009

Ironically, I think you need to first give it an input delay and then give it the false path...

 

Without the input_delay, the SELF_DONE is not a startpoint of a static timing path; the set_input_delay makes it one. Then you can declare it false

 

set_input_delay <any_value> -clock [get_clocks <any_clock>] [get_ports SELF_DONE]

set_false_path -from [get_ports SELF_DONE] -to [get_pins <some_path>/self_done_demet_reg[0]/D]

 

 

Avrum

 

 

View solution in original post

6 Replies
Highlighted
Scholar
Scholar
18,028 Views
Registered: ‎11-21-2013
Hi Tomalek,
I think what you want is to simply specify the source path:

set_false_path -from [get_ports SELF_DONE]

That's all.
Regards
Vlad
Vladislav Muravin
0 Kudos
Highlighted
Guide
Guide
28,449 Views
Registered: ‎01-23-2009

Ironically, I think you need to first give it an input delay and then give it the false path...

 

Without the input_delay, the SELF_DONE is not a startpoint of a static timing path; the set_input_delay makes it one. Then you can declare it false

 

set_input_delay <any_value> -clock [get_clocks <any_clock>] [get_ports SELF_DONE]

set_false_path -from [get_ports SELF_DONE] -to [get_pins <some_path>/self_done_demet_reg[0]/D]

 

 

Avrum

 

 

View solution in original post

Highlighted
Scholar
Scholar
18,010 Views
Registered: ‎11-21-2013

Avrum,

 

Can you please elaborate on this? We don't set_input_delay on the inputs we don't care about, and the timing analysis does return some path for the timing-excepted inputs using set_false_path.

 

Thank you

Vlad

Vladislav Muravin
0 Kudos
Highlighted
Guide
Guide
18,005 Views
Registered: ‎01-23-2009

We all agree that there is no need to constrain this path - an asynchronous single bit  signal going to a clock crossing circuit doesn't need to be constrained.

 

However, the OP asked how you can get this path removed from the list of unconstrained paths, and how to remove this input from the "no input delay" check of check_timing. If you don't have a set_input_delay on this input, then it shows up in both reports.

 

Apparently (and this makes some sense), you can't just do a set_false_path on it to remove it from these reports. Without a set_input_delay, it is not a path. So, to

  - leave it unconstrained and

  - to remove it from these reports

I suspect that what I suggested in the previous post will work.

 

Avrum

 

 

0 Kudos
Highlighted
Visitor
Visitor
17,579 Views
Registered: ‎07-16-2014

I can confirm that the solution suggested by avrumw worked:

 

set_input_delay <any_value> -clock [get_clocks <any_clock>] [get_ports SELF_DONE]

set_false_path -from [get_ports SELF_DONE] -to [get_pins <some_path>/self_done_demet_reg[0]/D]

 

Thanks for your help,

tomalek

Highlighted
Observer
Observer
2,226 Views
Registered: ‎05-21-2018

Found a better organized template to handle all the async inouts without any additional work.

Make the following template as the first file as it contrains section 0b which needs only one time and at first time.
Any other synchrnous interface will go to another file and will use the same template but without the 0a and 0b sections.

Here you go:


####################################################################################################
## This file has to be called first if you are overriding any synchronous interface in different file
## Section 0a)
# Clocks and generated clocks - sync clocks can be declared later / in another file
####################################################################################################

# don't need to define if pll input is clock capable pin - good to define if using ILA
create_clock -quiet -period 50.000 -name clk_in [get_ports {clk_in}]

# Generated clock aaa
create_generated_clock -quiet -name clk_aaa -source [get_pins clk_pll_i/inst/plle2_adv_inst/CLKOUT1] -divide_by 16 [get_pins ]

# Generated clock bbb
create_generated_clock -quiet -name clk_bbb -source [get_pins clk_pll_i/inst/plle2_adv_inst/CLKOUT1] -divide_by 1 [get_nets ]


#######################################################################################################
## Section 0b)
## Innovative way to handle all async inouts at one-shot from Vivado tool
# Create a clock async_inouts and make it asynchronous to all other clocks
# Apply all signals to async_inouts; over rides sync interfaces later after their clock declaration
# Also meta flops can have infinite delay - this can be overwritten if gray counter cdc or for better performance
#######################################################################################################

# 20ns period gives max delay of 20 ns for the pass through signals through fpga
# Defined 19.999 ns as a tag
create_clock -quiet -period 19.999 -name async_inouts

# Measure is treasure - use max delay instead of a ignored path (fase path/async group)
# help to analyze later if needed - 899.999 is used a tag for this kind
#set_clock_groups -async -group [get_clocks async_inouts]
set_max_delay -datapath_only -from [get_clocks async_inouts] -to [get_clocks clk*] 899.999
set_max_delay -datapath_only -from [get_clocks clk*] -to [get_clocks async_inouts] 899.999

# 0 inout delays makes max delay of 20 ns for the pass through signals through fpga
# if needed, later tighten the interested paths through max delay
set_input_delay -clock [get_clocks async_inouts] 0.000 [all_inputs] -quiet
set_output_delay -clock [get_clocks async_inouts] 0.000 [all_outputs] -quiet

# ASYNC_REG is set in RTL meta flops of cdc modules, clock to clock max delay is used already
# Relaxing the meta paths; if needed, later tighten the interested paths through max delay
# help to analyze later if needed - 799.999 is used a tag for this kind
set_max_delay -to [get_cells -hierarchical -filter {ASYNC_REG==1}] 799.999

##########################################################################################
## Section 1)
# Synchronous clocks and Overriding sync interfaces io delays afer clock declaration
# Ensure not to use -add_delay to override above generic constraint
##########################################################################################

set_output_delay -clock [get_clocks clk_aaa] 0.000 [get_ports io_output_ser_clk] -quiet
set_output_delay -clock [get_clocks clk_aaa] 0.000 [get_ports led_output_latch] -quiet


##########################################################################################
## Section 2)
# multi_cylce relax : between same clock, mainly needed for the pins of sync interfaces
# or for the large logic between flops if it will not affect functionality
##########################################################################################


##########################################################################################
## Section 3)
# max_delay optimum : last override, may not override later
# - tighten paths for better performance / to meet timing
##########################################################################################

 


##########################################################################################
## Section 4)
# false_path relax : this has the high precedence and use only for logical false paths
# paths are ignored in timing reports by default
##########################################################################################

 

##########################################################################################
## Section 5)
# Static constraints : single line constraints which are not depedednt on others
##########################################################################################

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]