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Participant saurabhsk
Participant
14,346 Views
Registered: ‎02-17-2009

How to write UCF for multiple clocks which may are may not be in same domain

Hi All,

 

   I am facing problem in specifying CLOCKS in UCF.

 

Lets say a case where i am having 2 clocks clk1 and clk2 , and output of clk1 is going to clk2 . ( Let's say this is the only design , without adding any synchronizer).

 

 Then from SDC i can say :

 

  create_clock {clk1 } -period 10 -waveform {0 5}

  create_clock {clk2 } -period 8 -waveform {0 5}

 

It's need not/don't want  to tell anything about domains here in SDC.

 

If i want to write same/equivalent constraints in UCF for XST , then how to do that. Because i think it asks to spoecify the domain as well, which i don't want.

 

Please help me out for the same ASAP.

 

-Saurabh

 

 

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11 Replies
Xilinx Employee
Xilinx Employee
14,334 Views
Registered: ‎11-28-2007

Re: How to write UCF for multiple clocks which may are may not be in same domain

You may find the information in the documents below useful. Search for PERIOD.

 

http://toolbox.xilinx.com/docsan/xilinx10/books/docs/cgd/cgd.pdf

 

http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf

 

 

Cheers,

Jim

Cheers,
Jim
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Participant saurabhsk
Participant
14,331 Views
Registered: ‎02-17-2009

Re: How to write UCF for multiple clocks which may are may not be in same domain

Thanks for the reply .

 

 So, as per doc i found that for SDC like :

 

 create_clock  {clk} -name clk1 -period 10.000000 -waveform { 0.000000 5.000000 }
create_clock  {clk1} -name clk2 -period 8.000000 -waveform { 0.000000 4.000000 }

 

 UCF will be looks like :

 

TIMESPEC TS_Period_1 = PERIOD "clk2" 8 ns HIGH 50%;
TIMESPEC TS_Period_2 = PERIOD "clk1" TS_Period_1 * 1.25;

 

  So, in UCF it is making both the clocks in same clock domain. But from SDC , this is not the case. There are 2 independent clock ports in the design and constraints.

 

 Youre suggestions will be really helpful.

 

-Saurabh

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Historian
Historian
14,318 Views
Registered: ‎02-25-2008

Re: How to write UCF for multiple clocks which may are may not be in same domain


saurabhsk wrote:

Thanks for the reply .

 

 So, as per doc i found that for SDC like :

 

 create_clock  {clk} -name clk1 -period 10.000000 -waveform { 0.000000 5.000000 }
create_clock  {clk1} -name clk2 -period 8.000000 -waveform { 0.000000 4.000000 }

 

 UCF will be looks like :

 

TIMESPEC TS_Period_1 = PERIOD "clk2" 8 ns HIGH 50%;
TIMESPEC TS_Period_2 = PERIOD "clk1" TS_Period_1 * 1.25;

 

  So, in UCF it is making both the clocks in same clock domain. But from SDC , this is not the case. There are 2 independent clock ports in the design and constraints.

 

 Youre suggestions will be really helpful.

 

-Saurabh


First -- what is "SDC"?

 

Second -- in that example you cite, clk1 is related to clk2 only because its clock frequency is a fraction of clk2's.  The clocks are NOT otherwise related and are NOT in the same "domain."

 

You could have written:

 

TIMESPEC TS_Period_1 = PERIOD "clk2" 8 ns HIGH 50%;
TIMESPEC TS_Period_2 = PERIOD "clk1" 10 ns HIGH 50%;

 

and the tools wouldn't know the difference.

 

-a

----------------------------Yes, I do this for a living.
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Participant jared.chen
Participant
14,296 Views
Registered: ‎05-12-2008

Re: How to write UCF for multiple clocks which may are may not be in same domain

Hi Saurabh,

 You may write below in UCF.

NET "clk1" TNM_NET = "clk1";

TIMESPEC TS_Period_1 = PERIOD "clk1" 10 ns HIGH 50%;

NET "clk2" TNM_NET = "clk2";

TIMESPEC TS_Period_2 = PERIOD "clk2" 8 ns HIGH 50%;

 

Actually, the synpify will generate a constaint file(.ncf) for Xilinx tools. The syntac of NCF is similar with the UCF.

 

P.S: The SDF is a Synplify constraint file.

 

Regards,

Jared

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Participant jared.chen
Participant
14,295 Views
Registered: ‎05-12-2008

Re: How to write UCF for multiple clocks which may are may not be in same domain

Sorry, I mean the SDC is a synplify constraint file.
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Xilinx Employee
Xilinx Employee
14,276 Views
Registered: ‎11-28-2007

Re: How to write UCF for multiple clocks which may are may not be in same domain

 SDC (Synopsys Design Constraint) is yet another acronym among millions of others we see everyday. ;)

 

Cheers,

Jim

 

 

Cheers,
Jim
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Participant saurabhsk
Participant
14,274 Views
Registered: ‎02-17-2009

Re: How to write UCF for multiple clocks which may are may not be in same domain

Now my point is that if my SDC is like :

 

   create_clock {clk1 } -period 10 -waveform {0 5}

  create_clock {clk2 } -period 8 -waveform {0 5}

 

 here i am not defining any domain . SO for any tool who is supporting SDC , will treat it as in same domain or in different domain.

 

If it will treat it as in same domain , then it will NOT analyze any false path b/w these two clocks.

 

If it is putting it in two different domain then it is automatically detect a false path b/w clk1 and clk2 and it will not do any timing analysis b/w them.

 

Now if we will write UCF like :

 

NET "clk1" TNM_NET = "clk1";

TIMESPEC TS_Period_1 = PERIOD "clk1" 10 ns HIGH 50%;

NET "clk2" TNM_NET = "clk2";

TIMESPEC TS_Period_2 = PERIOD "clk2" 8 ns HIGH 50%;

 

 We are forcing the tool to take clk1 and clk2 in two different group/domain . and it will detect false path b/w these clocks as well.

 

So it seems not be the equivalent UCF constraint  file for given SDC or My understading about how tool will take SDC constraints for timing analysis is wrong.

 

Please help me out for the same.

 

-Saurabh

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Xilinx Employee
Xilinx Employee
14,264 Views
Registered: ‎11-28-2007

Re: How to write UCF for multiple clocks which may are may not be in same domain

Not sure I understand your message.

 

Where do clk1 and clk2 come from?

Are their any paths between clk1 and clk2? If yes, do you want to have the timing analyzer check the timing on these paths?

 

Cheers,

Jim

Cheers,
Jim
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Participant saurabhsk
Participant
14,262 Views
Registered: ‎02-17-2009

Re: How to write UCF for multiple clocks which may are may not be in same domain

Clk 1 and clk2 is input port

 

 and logic is like 

 

module try (clk , clk1 , in , out , a,b,c,d,e);

input clk,clk1;
input in;
input a,b,c,d,e;
output out;

reg out;
reg temp;

wire temp1;

assign temp1 = (((a | b) ^ (c & d)) | e ) ^ temp;

always @(posedge clk)
begin
     temp <= in;

end



always @(posedge clk1)
begin
     out <= temp1;

end

endmodule

 

And corresponding SDC is :

 

 create_clock  {clk} -name clk1 -period 10.000000 -waveform { 0.000000 5.000000 }
create_clock  {clk1} -name clk2 -period 8.000000 -waveform { 0.000000 4.000000 } 

 

Now i am looking for the expected behavior of synthesis tool for timing analysis as i mentioned in my last note above and corresponding UCF for this SDC.

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Historian
Historian
5,758 Views
Registered: ‎02-25-2008

Re: How to write UCF for multiple clocks which may are may not be in same domain

Ummm, why don't you ask Synplicity your question?

 

-a

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
5,756 Views
Registered: ‎09-14-2007

Re: How to write UCF for multiple clocks which may are may not be in same domain

Hi,

 

I am not an SDC expert, although I have some ideas on this...

 

Bassman is correct. You probably want to talk to the vendor who uses SDC flow to learn more. I am guessing you are using this with Primetime or Synplify.

 

As Jim said, it all depeneds on what you are trying to achieve. Here is a snippet from the Primetime documentation:

 

CK1 and CK2 are
SYNCHRONOUS:

 create_clock -period 2 -name CK1 \
create_generated_clock -name CK2 \
[get_ports CKP1]
-source [get_ports CKP1] \
-divide_by 2 [get_pins U1/Q]

 

CK1 and CK2 are
ASYNCHRONOUS:

create_clock -period 2 -name CK1 \
[get_ports CKP1]
create_clock -period 6 -name CK2 \
[get_pins OSC/OUT]
set_clock_groups -asynchronous \
-group {CK1} -group {CK2}

CK1 and CK2 are
EXCLUSIVE:

create_clock -period 2 -name CK1 \
[get_ports CKP1]
create_clock -period 8 -name CK2 \
[get_ports CKP2]
set_clock_groups -logically_exclusive \
-group {CK1} -group {CK2}

 

 Along the same lines:

Two clocks are synchronous with respect to each other if they share
a common source and have a fixed phase relationship. Unless you
specify otherwise, PrimeTime assumes that two clocks are
synchronous if there is any path with data launched by one clock and
captured by the other clock. The clock waveforms are synchronized
at time zero.

 

Taking this to consideration I would say that you should create the UCF syntax that would show the relationship between the two clocks, if you want it to be anaylyzed. If no relationship is not established between the two clocks, then you will not get this anaylyzed by the timing tools.

 

 Please double check what I am saying wit Synopsys, as they are the experts on SDC.

 

Thanks

Duth

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