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Adventurer
Adventurer
507 Views
Registered: ‎11-18-2013

How to write a timing constraint for IDDR data

Hello,

       Our setup involves reading data from multiple ADC ICs giving out data in DDR (center aligned) mode. A clock distribution chip generates the reference clock for each ADC and also provides a clock to the FPGA. 

In order to synchronize the data from the ADCs our approach is as follows: use the reference clock from the CGEN chip to read data into the FPGA. The ref clock is 40MHz and a MMCM is used to generate a 100MHz clock. 

The ADC data and this 100MHz clock is fed to IDDR for recovering the individual data (so DDR data is at 200MSps). 

Please guide on how to write a OFFSET IN timing constraint using the MMCM generated clock.

Specifically:

SMA_CLK_P (40MHz) is the top level port/pin name which goes to a PLL and generates PLLCLK_CLKOUT0 (100MHz).

NET "SMA_CLK_P" TNM_NET = LMKCLK;

TIMESPEC TS_LMKCLK = PERIOD "LMKCLK" 40MHz HIGH 50%; 

The above constraints the external input clock. 

lets say the ADC data is named RFD_DIQ (std_logic_vector(11 downto 0)). 

INST "RFD_DIQ<?>" TNM = "IN_DATA";

TIMEGRP "IN_DATA" OFFSET = IN 1.0 ns VALID 2.0 ns BEFORE ?????;

Please advise on what should ???? be (should I give the net name of the MMCM clock?).

The theoretical value for time window for 100MHz DDR is 5ns so lets say 2.5ns before the rising edge and 2.5ns after. But to take into account the real world imperfections (jitter, rise time fall time etc. thanks to @avrumw for making me realize the signficance), the available window is modified to only 2ns (1ns before the rising edge and 1ns after the rising edge). 

Thank you for your help,

 

 

 

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3 Replies
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Guide
Guide
471 Views
Registered: ‎01-23-2009

There are a whole bunch of potential problems here...

If I understand correctly, each ADC gets a copy of the 40MHz clock, and generates a 200Msps output. I presume that it is also sending a 100MHz clock along with this 200Msps (DDR) data? If so, what are you doing with each of these 100MHz clocks? Ignoring them?

Unless this is a very unusual ADC, there is no way to capture the data from the ADC with the REFCLK (or a copy of the REFCLK). Even if the two were at the same clock frequency (which they are not), it is unlikely that that the REFCLK->DOUT PVT variation would be as small as 3ns (which is what you are budgetting with your OFFSET IN constraint), and even more unlikely that the valid window would be centered around the REFCLK. ADCs provide forwarded clocks for a reason! As is always the case, all timings written in a constraint file must be extracted from the datasheet of the sending device - only if the ADC has a specification for REFCLK->DOUT can you create a constraint based on that clock (and it would need to be derated due to the output to output skew of the clock distribution chip).

And the REFCLK is not at 100MHz it is at 40MHz. These aren't even integer multiples of each other - the PLLs are all multiplying by 2.5. Since this is a non-integer multiplication, I am pretty sure that the output is not unique - each PLL (including the MMCM) can end up with one of two possible 100MHz clocks which are 180 degrees apart from each other. Since this is a DDR interface, this may not matter, or it may interfere with framing.

So, assuming I understand your clocking scheme, I suspect that it is illegal, and hence constraints are irrelevant.

That being said, your question is valid - how do you constrain an input that is synchronous to a clock that is only related to an input clock that only has a phase relationship (not a frequency relationship). I am not 100% certain in ISE, but I think you can still specify the constraint with respect to the clock defined at the pin input - even though it is the wrong frequency. The tools should derive the requirement from the frequency of the clock at the output of the MMCM, but the phase with respect to the incoming 40MHz edge. But I am not certain, so you would have to try it and see. Incidentally, this is not an uncommon situation - HDMI does this - the data is sent at 14x (I think) the rate of the clock, but is phase locked to the clock...

Avrum

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Adventurer
Adventurer
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Registered: ‎11-18-2013

Thanks for the reply @avrumw 

I tried giving the input to the MMCM in the OFFSET IN constraints but the constraint wasn't applied. Please advise. 

Situation:

1) By changing the phase of the MMCM clock I am able to acquire data from different ADCs correctly (different phases for different ADCs). 

I would like to translate this to OFFSET in constraints (or some other constratint) so that I can read data from all ADCs with the same clock. Am I correct in my understanding here? 

Please adivse on how to proceed because OFFSET can only be used for external clock inputs. Further OFFSET does take into account phase delays contributed by DCM or PLLs (I assume these are MMCMs) but does it take into account frequency conversion also? 

 

2) The other approach would be to use IODELAYE1 blocks for each data input. However the maximum delay possible is 78ps x 32 = 2,496ps. This is a quarter of the period of my DDR data where the clock is 10,000 ps. So I suppose this is not the best approach at this low frequency (may be more suitable for higher data rates). 

In short I think placing the right constraints and letting the place and route tool take care of the timing might be the best and easiest approach. 

Thanks again,

 

 

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Guide
Guide
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Registered: ‎01-23-2009

As I mentioned in my previous e-mail, I highly suspect that what you are trying to do is illegal - it simply can't work. Its not a tool thing its an architecture thing. Constraints won't make any difference.

What ADC are you trying to use?

Avrum

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