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enrico.r
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Registered: ‎02-27-2019

I/O interface delay constraints in board file?

Hi all,

I'm working with a Zynq on a custom board, which has its own Vivado board file. The board uses a custom interface "FT601" which is used as I/O to an external device (FTDI FT601 chip). We've also developed an IP-Core which has an "FT601"-type port used to communicate to the external FTDI chip.

The I/O interface should have its own timing constraints (input & output delay). The following steps work:

  1. Create new project, select custom board file and create a block design
  2. Add the constraint file "FT601Constraints.xdc" to the project
  3. Run synthesis - everything works

The problem is that I have to manually add the file FT601Constraints.xdc to the project. How I can automatically set those I/O timing constraints?

The optimal solutions would be, in my opinion, to insert those constraints to the board file, since they are related to the length of PCB traces and the external device timing, which are related to the board itself (and not to the IP core nor to the interface definition).

Can I add those timing constraints to the board file? How I can do that?

If the timing constraints can not be added to the board file, which is the correct place to put them to be automatically loaded by Vivado when using that interface on my board? As a workaround I've also tried to add the constraints inside the IP-Core, but I could not succeed as the constraints added to the IP-Core seems to be "scoped" so I can not get the needed references to external clock and I/O ports.

Thanks

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blindobs
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Registered: ‎09-13-2018

Hi,

Adding *.xdc to board files is really bad idea - as you can see in /boards folder xilinx and other vendors don't do it, because it doesn'y make sense. XDC constraints are based on port IO names, there is no guarantee that user will name port in the same manner as in XDC file.

What you can do is adding FT601 interface to the board file with custom component that matches your IP, and add XDC file in your IP. Of couse XDC file in ip can reference I/O ports and external clocks - see some existing xilinx example ips
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enrico.r
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Registered: ‎02-27-2019


@blindobs wrote:

Of couse XDC file in ip can reference I/O ports and external clocks - see some existing xilinx example ips

Can you say more about this? Using directly get_clocks or get_ports doesn't seem to work, even if the xdc has USED_IN set to board. I've looked at axi_ethernet IP core which add I/O constraints but reverse engineering that module it's not so easy. If I've understood correctly the files board.xit and utils.tcl are supposed to do the trick but not sure how.

Is there any documentation about this?

Thank you

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blindobs
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Registered: ‎09-13-2018

In my simple IPCORE i use following code for constraining input/ouput ports

#*******************************************************************************
# input port constraint (Centerl aligned)
#*****************************************************************************
set input_interface_clock         [get_clocks -of_objects [get_ports CLOCK_i]];        # Name of input clock
set input_interface_clock_period  [get_property PERIOD $input_interface_clock];        # Period of input clock
set data_ts              10.000;                                                       # Data valid before the rising clock edge
set data_th              [expr $input_interface_clock_period/2 + 10.000];

# Input Delay Constraint
set_input_delay -clock $input_interface_clock -max  [expr $input_interface_clock_period - $data_ts] [get_ports DATA_i]
set_input_delay -clock $input_interface_clock -min $data_th [get_ports DATA_i]

#*********************************************************
# output port constraint (Centeral aligned)
#*********************************************************
create_generated_clock -name CLOCK_TX_FWRD -source [get_pins MYIPCORE/TX_DRIVER/clock_reg/Q] -divide_by 1 [get_ports  CLOCK_o]

set_output_delay -clock CLOCK_TX_FWRD -max [expr 2 + 10.000] [get_ports -prop_thru_buffers DATA_o];
set_output_delay -clock CLOCK_TX_FWRD -min [expr 0.000 - 10.000] [get_ports -prop_thru_buffers DATA_o];

 

xdc is used in ooc mode

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enrico.r
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Registered: ‎02-27-2019

Thank you for the fast reply.


@blindobs wrote:

xdc is used in ooc mod



Why ooc mode? If I understand correctly you suggest to set USED_IN = synthesis, implementation, out_of_context ? If I do so, as expected my xdc file is not even executed, since when I use my IP CORE in my design it is not an ooc synthesis.Maybe I miss something?

disegno.svg.png

 

 

 

That said I've continued with USED_IN = synth, impl. Referring to the figure I've wrote this simple XDC:

 

set ft_clk [get_clocks -of_objects [get_ports IPPORT_CLK]]
set_input_delay -clock $ft_clk -max 1.0 [get_ports IPPORT_A]

But while the clock is correctly recognized, for the port I got:

 

 

[Constraints 18-602] set_input_delay: list contains '1' objects of types '(pin)' other than the types '(input port,internal pin)' supported by the constraint. These objects will not be used for this constraint. Please review the object list and ensure unsupported object types are removed. ["... /Constrain.xdc":2]

[Constraints 18-472] set_input_delay: list does not contain any object of type(s) '(input port,internal pin)' supported by the constraint. The constraint will not be applied. Please check to make sure that this is intended. ["... /Constrain.xdc":2]

If I use IFPORT_A instead of IPPORT_A:

 

set ft_clk [get_clocks -of_objects [get_ports IPPORT_CLK]]
set_input_delay -clock $ft_clk -max 1.0 [get_ports IFPORT_A]

I got a different error:

 

 

[Vivado 12-4739] set_input_delay:No valid object(s) found for '-objects [get_ports IFPORT_A]'. ["... /Constrain.xdc":2]

To me it's unclear why it appends "-objects" before the [] brackets.

What am I doing wrong?

 

 

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