I need to implement a arithmetic,but the timing is not met, how can I fix it?

[retni]

The arithmetic is:

s[n] = s[n-1]*(1-c) + din[n]*c

And I need it run in 200MHz, but the timing report showed it was not met the timing.

My sysgen project is this

How can I improve the timing?

[nagabhar]

HI @retni

Are you facing setup violations? 
If the violations are internal to addsub module,

How  are you implementing the Addsub module? using Fabric or DSP48?
Double click on the Addsub, in the implementation tab , check the pipeline for maximum performance option.

share your slx file here if possible.

[bwiec]

That's a combinatorial loop. In any case, it's not correct to your equation. You need a register in your feedback path before Cmult1. That should solve both problems.

[retni]

I have tried the Fabric and DSP48 option, but could not meet the timing neither.

this is my slx

thanks~

[retni]

If I add a register before Cmult1, then the formula is not right, I think.

I have uploaded my .slx file before, can you please take a look at it? Thanks very much.

[bwiec]

Hello,

s[n] = s[n-1]*(1-c) + din[n]*c

This means the current output sample is dependent on the previous output sample. So you need to store the previous output sample in a register and that feeds the mult and finally the adder. The way you have it now, the current output sample is feeding the mult/adder.

[retni]

The CMult1 has 1 clock delay itself. So I can not add register which will add another delay.

[gszakacs · Accepted solution]

What you have run into is a problem with Infinite Impulse Response (IIR) filters.  This is why FIR filters are more typically used in an FPGA: even though they are more complex to implement, they can easily be pipelined since they don't depend on the most recent output of the filter, only on the last N inputs to the filter.  You may be able to pipeline the IIR filter, however it becomes more complex.  For example, you could re-define the equation to use the output from two cycles earlier as well as the most recent two samples.  Depending on the logic used to implement the filter, this may or may not help you to meet timing, since it adds more layers of logic as well as adding an additional pipeline stage.

[retni]

Thanks very much.

I use this equation to generate an adaptive threshold.

I think I can only run this algorithm on 100MHz on the zedboard....