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Newbie
Newbie
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Registered: ‎03-29-2020

I need to make clock divider by using verilog

module clockdivider(
input clk,
input rst,
output reg clk_operating
);
reg [3:0] count;

always @(posedge clk, posedge rst) begin
if(rst == 1'b1) begin
count <= 4'b0;
clk_operating <= 1'b0;
end
else begin count <= count + 4'b1; //??
clk_operating <= (count == 4'b0); //??
end
end
endmodule

 

I want to make a clock divider that divides frequency by 16.

I'm very first at coding Verilog and I can't find what I missed. How can I fix it?

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2 Replies
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Voyager
Voyager
299 Views
Registered: ‎06-28-2018

Re: I need to make clock divider by using verilog

Hi @aiyai 

You can use Clocking Wizard to divide a clock.

The problem with the code is that the clock goes HIGH only if the counter is 0 and then it goes back to LOW and stays LOW for 15 cycles. Duty cycle is not 50%. To fix it instead of using == you might want to use one of <, >, <=, >= there. Also you need to count up to 32 to divide the clock by 16.

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Mentor
Mentor
260 Views
Registered: ‎06-16-2013

Re: I need to make clock divider by using verilog

Hi @aiyai 

 

This is simple divider.

But I don't recommend to use it as FPGA source code.

The best way is using Clock Wizard to describe clock divider.

 

Best regards,

 

// Example code

module div_clk(

  input wire clk,

  output reg div2_clk,

  output reg div4_clk,

  output reg div8_clk,

  output reg div16_clk

);

 

always @(posedge clk) begin

  div2_clk <= ~div2_clk;

end

always @(posedge div4_clk) begin

  div8_clk <= ~div8_clk;

end

always @(posedge div8_clk) begin

  div16_clk <= ~div16_clk;

end

 

 

endmodule

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