03-29-2020 07:33 AM
output reg clk_operating
reg [3:0] count;
always @(posedge clk, posedge rst) begin
if(rst == 1'b1) begin
count <= 4'b0;
clk_operating <= 1'b0;
else begin count <= count + 4'b1; //??
clk_operating <= (count == 4'b0); //??
I want to make a clock divider that divides frequency by 16.
I'm very first at coding Verilog and I can't find what I missed. How can I fix it?
03-29-2020 08:29 AM - edited 03-29-2020 08:36 AM
You can use Clocking Wizard to divide a clock.
The problem with the code is that the clock goes HIGH only if the counter is 0 and then it goes back to LOW and stays LOW for 15 cycles. Duty cycle is not 50%. To fix it instead of using == you might want to use one of <, >, <=, >= there. Also you need to count up to 32 to divide the clock by 16.
03-29-2020 02:09 PM
This is simple divider.
But I don't recommend to use it as FPGA source code.
The best way is using Clock Wizard to describe clock divider.
// Example code
input wire clk,
output reg div2_clk,
output reg div4_clk,
output reg div8_clk,
output reg div16_clk
always @(posedge clk) begin
div2_clk <= ~div2_clk;
always @(posedge div4_clk) begin
div8_clk <= ~div8_clk;
always @(posedge div8_clk) begin
div16_clk <= ~div16_clk;