cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
1,178 Views
Registered: ‎11-17-2017

IBUFDS delay in different banks

Hi

I find that the IBUFDS delay in different banks is different when I report timing summary .For example ,in bank 34,the IBUFDS delay is 0.894ns,but in bank 33,the IBUFDS delay is 0.924ns.So what does make this difference?

board :zc706

tool versions:vivado 2015.4

0 Kudos
5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
1,138 Views
Registered: ‎11-30-2007

The IBUFDS delay number includes package delay associated with every pin.  Therefore, every pin is likely different.

0 Kudos
Highlighted
Adventurer
Adventurer
1,131 Views
Registered: ‎11-17-2017

I know every pin is likely different in fact.But when I report timing summary ,the same bank shows the delay is same.I just constraint the timing and the slack is right. 

0 Kudos
Adventurer
Adventurer
1,115 Views
Registered: ‎11-17-2017

 
33bank.jpg
34bank.jpg
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
1,102 Views
Registered: ‎05-14-2008

I checked H9 and D9 in the same Bank 34, the delays of the two are also different.

 

Do those differences bring any problem for you?

 

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
951 Views
Registered: ‎07-12-2018

When you run "report timing summary" in the GUI, there is a setting "Write results to file" on the Advanced Tab. Use this setting to save the result as a text file.

 

What's more, are you analyzing timing after Synthesis before Implementation? The post-synthesis timing analysis is not accurate but estimated. You can not say that your constraints are met or not just by estimation. I remember when surrfing on CCleaner Happy Wheels VLC I found something about the topic stating one's should rely on the post-route timing analysis, especially for set_input_delay/set_output_delay constraints

 

Then,you have to realize that random jitter is not the same as peak-to-peak jitter, and for the timing analysis of an input, peak-to-peak (or cycle-cycle) jitter is what matters. The two are related to eachother by the transition density and the tolerable bit error rate. For a "good" interface (1e-20 bit error rate) you multiply by something like 16, so your 2ps random jitter is really 32ps of peak-to-peak jittter.

 

0 Kudos