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Adventurer
Adventurer
844 Views
Registered: ‎11-17-2017

IBUFDS delay in different banks

Hi

I find that the IBUFDS delay in different banks is different when I report timing summary .For example ,in bank 34,the IBUFDS delay is 0.894ns,but in bank 33,the IBUFDS delay is 0.924ns.So what does make this difference?

board :zc706

tool versions:vivado 2015.4

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5 Replies
Xilinx Employee
Xilinx Employee
804 Views
Registered: ‎11-30-2007

Re: IBUFDS delay in different banks

The IBUFDS delay number includes package delay associated with every pin.  Therefore, every pin is likely different.

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Adventurer
Adventurer
797 Views
Registered: ‎11-17-2017

Re: IBUFDS delay in different banks

I know every pin is likely different in fact.But when I report timing summary ,the same bank shows the delay is same.I just constraint the timing and the slack is right. 

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Adventurer
Adventurer
781 Views
Registered: ‎11-17-2017

Re: IBUFDS delay in different banks

 
33bank.jpg
34bank.jpg
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Xilinx Employee
Xilinx Employee
768 Views
Registered: ‎05-14-2008

Re: IBUFDS delay in different banks

I checked H9 and D9 in the same Bank 34, the delays of the two are also different.

 

Do those differences bring any problem for you?

 

-vivian

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Visitor guru_xil
Visitor
617 Views
Registered: ‎07-12-2018

Re: IBUFDS delay in different banks

When you run "report timing summary" in the GUI, there is a setting "Write results to file" on the Advanced Tab. Use this setting to save the result as a text file.

 

What's more, are you analyzing timing after Synthesis before Implementation? The post-synthesis timing analysis is not accurate but estimated. You can not say that your constraints are met or not just by estimation. I remember when surrfing on CCleaner Happy Wheels VLC I found something about the topic stating one's should rely on the post-route timing analysis, especially for set_input_delay/set_output_delay constraints

 

Then,you have to realize that random jitter is not the same as peak-to-peak jitter, and for the timing analysis of an input, peak-to-peak (or cycle-cycle) jitter is what matters. The two are related to eachother by the transition density and the tolerable bit error rate. For a "good" interface (1e-20 bit error rate) you multiply by something like 16, so your 2ps random jitter is really 32ps of peak-to-peak jittter.

 

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