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Participant josemao0
Participant
314 Views
Registered: ‎07-02-2018

IDELAYE2 Kintex 7+ Improve tap delay?

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Hello *

I managed to use IDELAYE2 from Kintex Evaluation board with IDELAYCTRL in 400MHz(REFCLK) in order to get a tap delay of 39ps, so far so good. I have a doubt regarding if it is possible to improve such tap delay to get for example 20/10ps instead. I have been looking for some info but no clear sources yet. 

Is there any resource or configuration to do it?.

Thanks in advance for your time. 

Best regards, 

Mauricio

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1 Solution

Accepted Solutions
Historian
Historian
259 Views
Registered: ‎01-23-2009

Re: IDELAYE2 Kintex 7+ Improve tap delay?

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Is it possible to manage this fine tap delay using Kintex 7 Evaluation board and IDELAYE2/IDELAYCTRL primitives?.

No.

The maximim IDELAYCTRL clock frequency is 400MHz (and that is only available in -2 and -3 parts), which results in a 39ps delay per tap (on average). It is not legal to go faster than that.

It is important to note that the 32 delay taps in the IDELAY are not guaranteed to be equal - the 39ns is an average among all the 32 delays. Each individual delay will not vary much over PVT, but the magnitude of the first delay taps are larger than 39ns, and the later taps are less than 39ns. Vivado knows the magnitude of each tap, so it always uses an accurate delay for any tap value.

Avrum

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4 Replies
Xilinx Employee
Xilinx Employee
307 Views
Registered: ‎05-22-2018

Re: IDELAYE2 Kintex 7+ Improve tap delay?

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Hi @josemao0 

Tap delay value can be varied by selecting an IDELAYCTRL reference clock from the range specified in the 7 series FPGA Data Sheet.

Thanks,

Raj

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Participant josemao0
Participant
304 Views
Registered: ‎07-02-2018

Re: IDELAYE2 Kintex 7+ Improve tap delay?

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Hi Raj, 

Thanks for your prompt reply, 

I found there are three attribute for REFCLK in IDELAYCTRL: 200/300/400 MHz which allow to make tap delay of 78/52/39 ps. I am using the 400MHz attribute to get 39ps but I need finer tap delays, in the range of 10-20ps. Is it possible to manage this fine tap delay using Kintex 7 Evaluation board and IDELAYE2/IDELAYCTRL primitives?. Any configuration or other possibility to make it?

Thanks once again for your time, 

Best regards

Mauricio

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Xilinx Employee
Xilinx Employee
283 Views
Registered: ‎05-22-2018

Re: IDELAYE2 Kintex 7+ Improve tap delay?

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HI @josemao0 ,

I am not sure for 7 series, but fro spartan6 there used to be a formula to calculate the max tap delay, please check this AR#:

https://www.xilinx.com/support/answers/35783.html

Tahnks,

Raj

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Historian
Historian
260 Views
Registered: ‎01-23-2009

Re: IDELAYE2 Kintex 7+ Improve tap delay?

Jump to solution

Is it possible to manage this fine tap delay using Kintex 7 Evaluation board and IDELAYE2/IDELAYCTRL primitives?.

No.

The maximim IDELAYCTRL clock frequency is 400MHz (and that is only available in -2 and -3 parts), which results in a 39ps delay per tap (on average). It is not legal to go faster than that.

It is important to note that the 32 delay taps in the IDELAY are not guaranteed to be equal - the 39ns is an average among all the 32 delays. Each individual delay will not vary much over PVT, but the magnitude of the first delay taps are larger than 39ns, and the later taps are less than 39ns. Vivado knows the magnitude of each tap, so it always uses an accurate delay for any tap value.

Avrum

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