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gvirbila
Explorer
Explorer
4,476 Views
Registered: ‎07-01-2013

ILA timing issues

Can anyone tell my why I am receiving these timing errors? There are also unconstrained internal ILA endpoints?

 

GabrielILA_timing.png

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mcgett
Xilinx Employee
Xilinx Employee
4,459 Views
Registered: ‎01-03-2008

Looks like you are trying to clock the ILA at 500 MHz, that is a bit tough to close timing on and a good portion of the ILA core needs to operate at the speed as the logic it is observing.

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yashp
Moderator
Moderator
4,443 Views
Registered: ‎01-16-2013

Hi Gabriel,

Can you give us more inputs on which signal, at what frequency you are trying to capture? Did you tried ILA by enabling the pipeline_register (while configuration you can enable it). After enabling the pipeline stage mostly you will see the violation on 1st register due to CDC and you can safely ignore or hide using false path (only applicable for 1st stage register as this helps for synchronization).

Thanks,
Yash
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arpansur
Moderator
Moderator
4,439 Views
Registered: ‎07-01-2015

Hi @gvirbila,

 

Are you using default implementation strategy? If so can you please try with other timing strategies as the slack are less?

Thanks,
Arpan
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