12-19-2013 05:57 AM
when i use vivado 13.3 set up a soc system,and use the ILA core to debug my design,it always failed implement with timing constraint, the clk frequence of the ILA is 125mhz, is it too high? but it's normal in FPGA design,can anybody help me???
12-19-2013 06:19 AM
What error are you getting? You mean to say due to ILA your deisgn is not able to meet timing?
Have you given a try without ILA?
12-19-2013 09:15 AM
12-19-2013 07:49 PM
the error message :
[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.
after implement , the resource usage is properly low, LUT 8%, BRAM 2%...,the ILA core just capture 43 signals
without the ILA,all constraints are met.
my prj use a ps_system as a submodule,and a AXI stream fifo IP also a submodule, i connect them in my top hdl files, so the constraint files should automaticly add to prj, and i saw the timing constraint below in the ps xdc file:
create_clock -name clk_fpga_0 -period "8" [get_pins "PS7_i/FCLKCLK"]
set_input_jitter clk_fpga_0 0.24
#The clocks are asynchronous, user should constrain them appropriately.#