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lostbooker
Observer
Observer
10,401 Views
Registered: ‎12-09-2013

ILA3.0 with vivado 13.3, failde in implement

when i use vivado 13.3 set up a soc system,and use the ILA core to debug my design,it always failed implement with timing constraint, the clk frequence of the ILA is 125mhz, is it too high? but it's normal in FPGA design,can anybody help me???

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4 Replies
pratham
Scholar
Scholar
10,398 Views
Registered: ‎06-05-2013

Hello,

 

What error are you getting? You mean to say due to ILA your deisgn is not able to meet timing?

 

Have you given a try without ILA?

 

-Pratham

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sampatd
Scholar
Scholar
10,390 Views
Registered: ‎09-05-2011

The clock signal connected to the clk port of ILA should be properly constrained. The product guide does not specifically mention any maximum frequency. Make sure that the clock you are giving to ILA is synchronous to the clock of your design.

What sort of timing violations do you see?


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lostbooker
Observer
Observer
10,381 Views
Registered: ‎12-09-2013

the error message :

[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.

 

after implement , the resource usage is properly low, LUT 8%, BRAM 2%...,the ILA core just capture 43 signals

 

without the ILA,all constraints are met.

 

my prj use a ps_system as a submodule,and a AXI stream fifo IP also a submodule, i connect them in my top hdl files, so the constraint files should automaticly add to prj, and i saw the timing constraint below in the ps xdc file:

create_clock -name clk_fpga_0 -period "8" [get_pins "PS7_i/FCLKCLK[0]"]
set_input_jitter clk_fpga_0 0.24
#The clocks are asynchronous, user should constrain them appropriately.#

 

i'm confused...

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lostbooker
Observer
Observer
10,380 Views
Registered: ‎12-09-2013

please see the post below,thank you so much
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