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Visitor
Visitor
9,246 Views
Registered: ‎08-07-2013

IO offset question

Hello,

 

I  generated a asynchronous clock CLKB by DCM_CLKGEN from CLKA,  and used CLKB to latch the input data "DA" and output data "DB", my question is how to contrain "DA" and "DB" IO offset relative to CLKB?

 

Thanks in advance

 

 

 

 

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Xilinx Employee
Xilinx Employee
9,236 Views
Registered: ‎05-14-2008

You need offset IN constraint for DA and offset out constaint for DB. However, the clock you should use in the OFFSET in and OFFSET out constraints is CLKA but not CLKB. The propagation path from CLKA to CLKB will be taken care of automatically by the Timing Analyzer tool.

 

For the syntax and usage of OFFSET constriants, please refer to "Constraints Guide" and "Timing Constraints Guide".

-Vivian

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Moderator
Moderator
9,234 Views
Registered: ‎01-16-2013

Hello,

 

CLKB is generated clock by DCM. and CLKA is input clock of DCM then it cannot be async clock.

Regarding IO offset question : Which tool you are using? 

If ISE : http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf refer offset out and offset in constraints.

 

Thanks,

Yash

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Xilinx Employee
Xilinx Employee
9,224 Views
Registered: ‎08-01-2012

The following user guide http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf also give some basic information information  in case of using older ISE tools like ISE10.X

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