06-11-2014 02:19 AM
I generated a asynchronous clock CLKB by DCM_CLKGEN from CLKA, and used CLKB to latch the input data "DA" and output data "DB", my question is how to contrain "DA" and "DB" IO offset relative to CLKB?
Thanks in advance
06-11-2014 02:55 AM
You need offset IN constraint for DA and offset out constaint for DB. However, the clock you should use in the OFFSET in and OFFSET out constraints is CLKA but not CLKB. The propagation path from CLKA to CLKB will be taken care of automatically by the Timing Analyzer tool.
For the syntax and usage of OFFSET constriants, please refer to "Constraints Guide" and "Timing Constraints Guide".
06-11-2014 02:58 AM
CLKB is generated clock by DCM. and CLKA is input clock of DCM then it cannot be async clock.
Regarding IO offset question : Which tool you are using?
If ISE : http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf refer offset out and offset in constraints.
06-11-2014 05:11 AM - edited 06-11-2014 05:13 AM
The following user guide http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf also give some basic information information in case of using older ISE tools like ISE10.X