I have to maintain a Spartan-6 design, so this is a question dealing with ISE.
I wish to relax timing on a set of signals crossing an asynchronous clock domain boundary. I don't want to use the open-ended TIG on them because there needs to be a maximum delay from a flip-flop in one domain to the flip-flop in the other domain. I am currently using this:
TIMESPEC TS_CLK1_TO_CLK2 = FROM FFS("u_clock1_logic/*") TO FFS("u_clock2_logic/*") 64 ns DATAPATHONLY;
With that constraint, I get large hold time violations. This is consistent with UG625 which says, “From synchronous paths, a From To constraint controls only the setup path, not the hold path.”
So my question: How do I get the ISE tools to ignore the hold time for these paths but still obey a maximum delay?