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Observer
Observer
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Registered: ‎10-26-2017

ISE - How to constrain clock with poor frequency accuracy (+/- 3)?

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For analog-world reasons we are using a 40 MHz oscillator with a terrible frequency accuracy of +/- 3% for part of our design (LTC6905). I just want to make sure I'm constraining this correctly so it will work over PVT, which is important to our design.

 

Intuitively, I would assume I could just constrain the clock as if it were 41.2 MHz, since its cycle-to-cycle jitter and stability over time are relatively low. Is this correct? Or will I violate hold times if I'm running at the minimum frequency of 38.8 MHz?

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: ISE - How to constrain clock with poor frequency accuracy (+/- 3)?

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You got it:

 

The minimum period is what is needed.  So the max frequency is the min period.  Depending on how old your ISE is, you may also need to trim the period smaller based on the peak jitter.  Later ISE has an input for clock and system jitter.  Make sure you set these values if in your ISE.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
2,044 Views
Registered: ‎02-27-2008

Re: ISE - How to constrain clock with poor frequency accuracy (+/- 3)?

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You got it:

 

The minimum period is what is needed.  So the max frequency is the min period.  Depending on how old your ISE is, you may also need to trim the period smaller based on the peak jitter.  Later ISE has an input for clock and system jitter.  Make sure you set these values if in your ISE.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Guide
Guide
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Registered: ‎01-23-2009

Re: ISE - How to constrain clock with poor frequency accuracy (+/- 3)?

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Or will I violate hold times if I'm running at the minimum frequency of 38.8 MHz?

 

In a simple synchronous system, the hold time requirement is independent of the clock frequency. In systems where the source and destination flip-flop are clocked by the same clock, the hold requirement is always 0.

 

However, if you start doing "fancy" stuff - crossing data between different phases of the clock (for example using a 0 degree and 30 degree phase shifted version of your clock), the hold times are "worse" at the faster clock rates. But in these cases, the hold requirements are already negative (they are just less negative at faster clock rates) - generally, the tools will not need this. But, they can (in theory) use it, so there is the very small possibility of underconstraint here - if you were really paranoid, you could adjust for it by increasing the clock jitter specification, or putting some extra inter-clock latency variation on it... But generally, in the main part of the design, none of this matters - one doesn't tend to use multiple phases of the same clock, and if we do, they tend to be pretty far out of phase so that hold time failures become impossible.

 

Where it can matter is in the timing of your interfaces - particularly if you are using phase shifted clocks for capture. Often input interfaces need to be optimized to maximize (or satisfy) larger setup and hold requirements. If you assume only the fastest clock, you can have less margin on your hold times. It is something to consider (but, again, tends not to be a huge thing).

 

Avrum

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Observer
Observer
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Registered: ‎10-26-2017

Re: ISE - How to constrain clock with poor frequency accuracy (+/- 3)?

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OK, thanks for the reassurance. Only one phase here, although I have nightmares of struggling to track down timing issues last summer when I was passing data between four phases of a 200 MHz clock. This question feels stupidly simple by comparison!

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