UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
13,169 Views
Registered: ‎09-18-2007

ISE Ignoring Multicycle constraints

I had a design running at 125MHz (8ns) and a certain part of logic takes 8.5ns. Thats fair enough, its a large calculation, but the inputs are static and I have many clock cycles to read the output. As it was slowest path, I could not see if there were any real paths to worry about, so I added a multicycle constraint from the source register to the output register. When I re-run PAR its still saying that the longest path is the one described here.

 

I raised a webcase by the reply was to use a half rate clock from the DCM. Well, OK, I could do this, but why should I have to complicate my design to bypass the tools? What if I had to divide by a very large factor outside the DCM divide range. Surely the whole point of the multicycle constraint is to mask out my above timing problem?

 

I'm finding the Timing Analyser not very intuative and my boss won't pay for PlanAhead which look so much easier when I tried the 60 day eval version.

 

Is there a manual for TA?

 

Thanks

 

0 Kudos
10 Replies
Xilinx Employee
Xilinx Employee
13,139 Views
Registered: ‎11-28-2007

Re: ISE Ignoring Multicycle constraints

Can you post your multicycle path constraints and the worst timing paths reported by timing analyzer?

 

 

By the way, in 10.1, ISE includes PlanAhead Lite, which has most of features in the full PlanAhead.

 

 

Cheers,

Jim

 

Cheers,
Jim
0 Kudos
Adventurer
Adventurer
13,127 Views
Registered: ‎09-18-2007

Re: ISE Ignoring Multicycle constraints

NET "SYS_CLK" TNM_NET = SYS_CLK;

TIMESPEC TS_SYS_CLK = PERIOD "SYS_CLK" 8 ns HIGH 50%;

 

 

TIMESPEC TS_IP_CSUM_LENGTH_MS = FROM "TMGRP_INNER_IP_PACKET_LENGTH" TO "TMGRP_INNER_IP_HDR_CSUM" TS_SYS_CLK * 2;

TIMESPEC TS_IP_CSUM_ID_MS = FROM "TMGRP_IP_INNER_SUCKS" TO "TMGRP_INNER_IP_HDR_CSUM" TS_SYS_CLK * 2;

 

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<0>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<1>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<2>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<3>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<4>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<5>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<6>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<7>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<8>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<9>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<10>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

 

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<0>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<10>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<10>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<11>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<11>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<12>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<12>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<13>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<13>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<14>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<14>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<1>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<1>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<2>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<2>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<3>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<3>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<4>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<4>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<5>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<5>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<6>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<6>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<7>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<7>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<8>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<8>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<9>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_cy<9>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_lut<0>" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/Mcount_IP_INNER_PACKET_ID_S_xor<15>_rt" TNM_NET = TMGRP_IP_INNER_SUCKS;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<11>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<12>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<13>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<14>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<15>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<16>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<17>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<18>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S<19>" TNM_NET = TMGRP_INNER_IP_HDR_CSUM;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<0>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<1>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<2>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<3>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<4>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<5>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<6>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<7>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<8>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<9>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<10>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<11>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<12>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<13>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<14>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

NET "U_DOWNLINK_PROCESSOR/U1/IP_PACKET_LENGTH_S<15>" TNM_NET = TMGRP_INNER_IP_PACKET_LENGTH;

 

 

The logic is clocked from a signal "CLK" that is the CLKx0 output of a DCM clocked with "SYS_CLK". When I set constraints in the GUI, it only recognises the input to the DCM as a clock rather than the output so I assume the software takes the DCM into account.

 

You'll notice the sucks comment. I tried adding the synthesis signals version of IP_INNER_PACKET_ID_S in case the tool only recognised them.

 

Thanks

 

 

Timing Error Report.JPG
0 Kudos
Xilinx Employee
Xilinx Employee
13,119 Views
Registered: ‎11-28-2007

Re: ISE Ignoring Multicycle constraints

The way TMGRP_IP_INNER_SUCKS and TMGRP_INNER_IP_HDR_CSUM are written is not right. Please take a look at the "Groups by Element" section under "Identifying Multi-Cycle and Fast or Slow Timing Assignments" in Chapter 4  Timing Constraint Strategies in Constraint Guide(http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf) . Also note wildcards and qualifiers can be used to write constraints.

 

As an example, for the source FF in your timing report, you can use the constraint below: 

 

 

INST "U_DOWNLINK_PROCESSOR/U1/IP_HDR_SUM_S_*" TNM = TMGRP_INNER_IP_HDR_CSUM;

 

Cheers,

 

Jim

Cheers,
Jim
0 Kudos
Xilinx Employee
Xilinx Employee
13,082 Views
Registered: ‎08-10-2008

Re: ISE Ignoring Multicycle constraints

The paths reported in the timing report are actually not covered by your multicycle constraints.
0 Kudos
Adventurer
Adventurer
13,072 Views
Registered: ‎09-18-2007

Re: ISE Ignoring Multicycle constraints

Thanks Jim, that now works and all constraints are met,  but why do I have to use INST rather than NET though?

 

I now note that it passes but the clock period is 8ns and the max delay is 7.999ns... Seems a bit of a coincidence and virtually no margin! I bet my 125MHz clock will not be exactly 125MHz - and what about jitter... I stepped up the effort from standard to medium and saw no improvment. The worst case path delay is now 0.813ns logic and 7.126ns routing! I cannot pipeline this path as its from an IP core and demands the data on the next clock edge.

 

Any ideas please???

0 Kudos
Xilinx Employee
Xilinx Employee
13,057 Views
Registered: ‎11-28-2007

Re: ISE Ignoring Multicycle constraints

The NET method groups synchronous elements driven by the net. It doesn't include synchronous elements driving the nets.

 

Which device are you targetting?

 

Cheers,

Jim

 

Cheers,
Jim
0 Kudos
Adventurer
Adventurer
13,055 Views
Registered: ‎09-18-2007

Re: ISE Ignoring Multicycle constraints

XC4VFX100-11 FG1517 I
0 Kudos
Adventurer
Adventurer
13,054 Views
Registered: ‎09-18-2007

Re: ISE Ignoring Multicycle constraints

I set the clock constraint to 7.5ns (133MHz) and the worst case timing is now 7.3ns. So does PAR change the way it runs according to the constraints? How can I know how much actual headroom I have other than bycontinually re-running the PAR - run it with no constraints....but then how much effort does it use...

 

Thanks

0 Kudos
Xilinx Employee
Xilinx Employee
13,044 Views
Registered: ‎11-28-2007

Re: ISE Ignoring Multicycle constraints

For Virtex4, the calculation of slack on FROM:TO constraint also takes the clock uncertainty/skew into to account.

 

> I set the clock constraint to 7.5ns (133MHz) and the worst case timing is now 7.3ns. So does PAR change the way it runs according to the constraints?

 

Yes, that's the whole point of constraining the design.

 

> How can I know how much actual headroom I have other than bycontinually re-running the PAR - run it with no constraints....but then how much effort does it use...

 

Why would you want run par w/o constraints? You should start with the speed requirement on the i/f and then constraint your design accordingly.

 

Cheers,

Jim

 

 

 

Cheers,
Jim
0 Kudos
Contributor
Contributor
4,831 Views
Registered: ‎09-10-2008

Re: ISE Ignoring Multicycle constraints


jimwu wrote:

For Virtex4, the calculation of slack on FROM:TO constraint also takes the clock uncertainty/skew into to account.

 

> I set the clock constraint to 7.5ns (133MHz) and the worst case timing is now 7.3ns. So does PAR change the way it runs according to the constraints?

 

Yes, that's the whole point of constraining the design.

 

I thought the same until today, but at least for OFFSET IN constraints it does not hold true.

 

Adding OFFSET IN constraints did not change ANY delay in any paths in my project , I checked it many times in FPGA editor today.

 So, to meet timing I had to manually tune IFD_DELAY_VALUE for input buffers, and PHASE_SHIFT for DCM.

 

Very disappoining, I thought the tools were more clever.

 

0 Kudos