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Visitor
Visitor
1,143 Views
Registered: ‎02-04-2018

ISE don't fix the hold time violation

The design requires the address been latch up by the clock, both the address and clock are from outside the FPGA. Since the logic is very simple, the data path delay is low, while the clock delay is relatively high, the hold violation occurs. I put following constrains, but the tools can not fix it.

 

The constrain is as following,

NET "clk" TNM_NET = clk;
TIMESPEC TS_sysclk = PERIOD "clk" 20 ns HIGH 10 ns INPUT_JITTER 500 ps;
OFFSET = IN 18 ns VALID 20 ns BEFORE clk;

 

The timing report about the hold time violation

 Hold Paths: OFFSET = IN 18 ns VALID 20 ns BEFORE COMP "clk";
 --------------------------------------------------------------------------------
 
 Paths for end point Rd_Addr_latch_2 (ILOGIC_X1Y98.D), 1 path
 --------------------------------------------------------------------------------
 Slack (hold path):      -1.455ns (requirement - (clock path + clock arrival + uncertainty - data path))
   Source:               Rd_Addr<6> (PAD)
   Destination:          Rd_Addr_latch_2 (FF)
   Destination Clock:    clk_BUFGP rising at 0.000ns
   Requirement:          2.000ns
   Data Path Delay:      0.547ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
   Clock Path Delay:     3.751ns (Levels of Logic = 2)
   Clock Uncertainty:    0.251ns
 
   Clock Uncertainty:          0.251ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
     Total System Jitter (TSJ):  0.050ns
     Total Input Jitter (TIJ):   0.500ns
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
   Minimum Data Path at Slow Process Corner: Rd_Addr<6> to Rd_Addr_latch_2
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     L1.I                 Tiopi                 0.688   Rd_Addr<6>
                                                        Rd_Addr<6>
                                                        Rd_Addr_6_IBUF
     ILOGIC_X1Y98.D       net (fanout=1)        0.000   Rd_Addr_6_IBUF
     ILOGIC_X1Y98.CLK     Tiockd      (-Th)     0.141   Rd_Addr_latch<2>
                                                        Rd_Addr_latch_2
     -------------------------------------------------  ---------------------------
     Total                                      0.547ns (0.547ns logic, 0.000ns route)
                                                        (100.0% logic, 0.0% route)
 
   Maximum Clock Path at Slow Process Corner: clk to Rd_Addr_latch_2
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     D5.I                 Tiopi                 0.823   clk
                                                        clk
                                                        clk_BUFGP/IBUFG
     BUFGCTRL_X0Y31.I0    net (fanout=1)        1.525   clk_BUFGP/IBUFG
     BUFGCTRL_X0Y31.O     Tbccko_O              0.076   clk_BUFGP/BUFG
                                                        clk_BUFGP/BUFG
     ILOGIC_X1Y98.CLK     net (fanout=58)       1.327   clk_BUFGP
     -------------------------------------------------  ---------------------------
     Total                                      3.751ns (0.899ns logic, 2.852ns route)
                                                        (24.0% logic, 76.0% route)
 
 --------------------------------------------------------------------------------

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Moderator
Moderator
1,091 Views
Registered: ‎01-16-2013

Hi,

Your clock path delay is too high and main reason for hold violations.
Can you try using different clocking for you interface? Like PLL/MMCM?

Also you can add IDELAY in data path to push the data and utilize the setup slack (I hope its good positive slack) to meet hold.

Thanks,
Yash
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Guide
Guide
1,084 Views
Registered: ‎01-23-2009

This question was answered in this forum thread.

 

Avrum

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