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Registered: ‎02-08-2017

ISE timing_analysis from command line, to/from a pin

I'm using ISE for Spartan 6. Launching from a batch file as I'm automating my analysis using scripts.

I'm able to script the creation of a timing analysis from a pin (pad) to a flip-flop (example script below) and produce a timing report file (.twx), however there are 2 possible paths from my pad to my FF, one to the clk pin and one to the din pin.

What I want to do next is to do my analysis so that it is from the pad to juts one pin, then a secons analysis from the pad to the other pin. This will create two .twx files which will be easy to analyse afterwards (probably using a Python script to find one max delay from each file).

I've attached a simplified schematic.

I’m calling the ISE Tcl shell from a Windows batch file:

C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\xtclsh rogers_timing_commands.tcl

My Tcl script file is:

#Project name (.xise file)
set myProject “MyProjectName"

#Analysis type: auto_generated | clock_io | endpoints | timing_constraint
set an_type endpoints

#Query type: net | timegroup
#Not used – not using a query

#Name for the timing analysis / query
set timing_name “MyTimingAnalysis”

#Name of the source input port (pad) – this is bit 0 of bi-directional io_data(7 downto 0)
set from_pad io_data<0>

#Name of destination FF. Note: [0] has been replaced by \[0\]
set to_ffs decode_inst/gen_block_a.generator/ports\[0\].decode_1/bit0decode/LATCH_R_1

project open $myProject

timing_analysis new analysis -name $timing_name
timing_analysis set $timing_name analysis_type $an_type
timing_analysis set $timing_name report_datasheet False
timing_analysis set $timing_name paths_per_constraint 10

# To/from, can be: ffs | pins | pads | nets
timing_analysis set_endpoints $timing_name from pads $from_pad
timing_analysis set_endpoints $timing_name to ffs $to_ffs

timing_analysis run $timing_name

timing_analysis delete $timing_name
project close


This all works fine, but when I try to do:

set to_pin decode_inst/gen_block_a.generator/ports\[0\].decode_1/bit0decode/LATCH_R_1/C
timing_analysis set_endpoints $timing_name to pins $to_pin


set to_pin decode_inst/gen_block_a.generator/ports\[0\].decode_1/bit0decode/LATCH_R_1/D
timing_analysis set_endpoints $timing_name to pins $to_pin

then I get the warning message:

WARNING:TimingToolsC - "decode_inst/gen_block_a.generator/ports\[0\].decode_1/bit0decode/LATCH_R_1/D" is not a valid Pin name.


Please help me to understand how to define the timing_analysis to pins command.


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1 Reply
Registered: ‎07-18-2018

Hi @r.smith,

  It's been a real long time since i did anything with ISE timing. But if there is an issue with how it's getting the paths, it looks like you are doing PlanAhead with tcl to call the timing tool with the pins:

do any variables for pins like:

set dst_pin [get_pins <name to the pin>]

As I recall it being more fickle back then about string names of elements in the netlist.

I don't know if that will resolve it. But it's worth giving a try.

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